EDN's 19th Annual Innovation Awards

Two of Cadence system D&V products have been selected as the finalists for the EDN innovation award: Palladium DPA (Dynamic Power Analysis) and C-to-Silicon Compiler. I went to the award Dinner this week. In the entrance, I have met Ron Wilson who told me that he believes in the current economic situation, high-level synthesis has a lot of promise since customers are looking for cost saving and productivity and therefore likely will be interested in such a product. As we have got in, I realized there are not too many recognized faces. When I looked at the whole list of categories, I have realized that out of almost 30 categories, only four of them cover the EDA market however I bet with you, each one of these products is using EDA tools as part of the development. This again confirms the level of dependency, the electronics industry has, in EDA products although the EDA industry is relatively small. As a person who was involved with HW products for many years (and still is today),  it was interesting to see the variety of HW products (many of them addressing power) that were presented in this award dinner.

The ceremony was organized very well and 4 EDA products won the final awards. One of them was Palladium DPA in the design analysis (which I was very proud of). Surprisingly (or maybe not surprisingly) Cadence, Synopsys, Mentor and The MathWorks (who was added to the EDA industry by EDAC in the last few years) won a single award each. I was also wondering why C-to-Silicon Compiler (high-level synthesis product) was competing at the same category (called design creation and IP) with a chip-level router tool?

In any case, it was my honor to see one of the products (Palladium DPA), I am responsible for, winning the final award and especially kudos to the development team  whao innovated a lot in this product. If you are interested to know more about Palladium DPA, Maulik Patel, Product Marketing Manager published an article explaining this product in details: Introducing Dynamic Power Analysis (Using High-Performance System-Level Power Estimation to Build Leaner, Meaner, and Greener Products).

If you want to get more details about both C-to-Silicon, Palladium DPA and Cadence system low-power solution sign-up for one of the local events at:  http://www.secure-register.net/cadence.php?product=8.

Ran Avinun