Emulation vs. FPGA Prototyping

There is a continuous debate about FPGA prototyping vs. emulation. This debate is heating-up with the latest Synopsys acquisitions of FPGA prototyping tools: Synplicity and Chip-It. This debate sometimes reminds me the endless debate between ASIC and FPGA companies. The reality is that there is a market for both. The FPGA prototyping segment addresses mostly validation of smaller designs or a single IP while emulation is being used for large SoC designs. The FPGA prototyping being used mostly for SW development while emulation is being used for HW/SW verification and full system validation. In the last 10 years, Cadence made emulation very easy-to-use with bring-up and turnaround times reaching simulation environment bring-up (and in some cases, becoming even better). Don't be foolish and look only at the initial cost in order to make your decision. Take in consideration, the resources, ease-of-use, time-to-market, risk mitigation and all the parameters being considered for any engineering project. Our customers continue to use emulation with the highest-level of satisfaction in the market and many new customers starting to use emulation every year as a result of the following parameters:

1. Fast bring-up time

2. Fast compile times (from RTL to run-time)

3. Superior debug

4. Rich SpeedBridge portfolio

5. Low cost of ownership

6. Scalability with high capacity and multi-user capability

7. Ease-of-use

 See below some of the recent testimonials from our customers who have chosen emulation vs. FPGA prototyping:

1. In the press release below, Hiroshi Kubo, division deputy general manager of the System Device Division at Sharp said:

"The Palladium system enabled our new methodology while making it easier and faster to build a verification environment than with our traditional system validation with breadboards, which we mainly used in the past.

http://www.cadence.com/cadence/newsroom/press_releases/Pages/pr.aspx?xml=020909_sharp 

2. Novafora, a startup company working on a video processor with several millions gates, is able to bring up their design on Palladium and discover significant architecture bugs before even committing to silicon, doing it in two to three weeks with Palladium, what would take two to three months with FPGA prototyping.

http://74.125.47.132/search?q=cache:YDr0U5p1DSUJ:seekingalpha.com/article/118597-cadence-design-systems-inc-q4-2008-earnings-call-transcript%3Fpage%3D-1%26find%3Dnow%26+novafora+cadence&hl=en&ct=clnk&cd=4&gl=us&page=3

 If you have comments, I will love to get your feedback.