In Verification, Failing to Plan = Planning to Fail

So I know you tell your kids this, you tell your spouse this, you heard it from your parents and they from theirs, yet somehow when it comes down to it -- it always seems easier to "do" than to "plan."  Even redo seems easier than to actually spend the time to write out a meaningful plan and then execute to it.  So why does the recent Cadence verification news revolve around the verification plan?

Because it is exactly what is needed to be successful with increasingly complex FPGA and ASIC designs! With the advent of and soon massive proliferation of the Universal Verification Methodology (UVM), this concept is even more critical than ever before.  Why? The power of UVM allows you to literally outstrip your ability to use it, as you can generate more information than you can consume if you're not careful. 

Imagine a 5,000 page newspaper with no structure, no sections, no headings, no article titles, and search that only returns the 3 words surrounding your query -- how would you navigate to the top story? Maybe you are interested in that small obituary story on VMM (just kidding), but how would you quickly find it? Now imagine 5,000,000,000 pieces of randomly generated coverage information. You have no idea how to navigate to the most meaningful part -- the headline story, or where you should focus your attention.  The point is, failing to plan is equal to planning to fail, and a good plan requires structure, hierarchy, the ability to quickly navigate to the most important sections, and ability to quickly compare the results to the goal and determine if you're done yet.

Any management process needs clear and measurable goals, and verification is no exception. Failing to capture these goals at the outset of a project means that there is no clear definition against which to measure either progress or closure. You can only gauge improvement in what you can clearly measure. Historically this was a problem with directed testing. Huge lists would be drawn up to define the verification process, but these lists were not executable or maintainable. This open-ended nature led to big project slips and huge stresses on project teams.   The advent of "coverage" gave us metrics to measure against, the advent of UVM gave us automation to more efficiently find bugs and create coverage, and the advent of Metric Driven Verification (MDV) gave us automation and a mechanism to make UVM truly useful. 

One of the single biggest components of MDV is creating the executable verification plan (vPlan), which is fully automated within a specific function of Incisive Enterprise Manager called Enterprise Planner.  Users of the Enterprise Planner capability now also have the ability to have multiple copies of Enterprise Planner operating together,- enabling team based verification plan creation, editing, review and sign off.   Now project managers, designers, multiple verification engineers, can all contribute their own expertise to the verification plan, improving its effectiveness and ultimately the quality of your design.

So if you're not planning to fail, check out the new Enterprise Planner capability on your next project, and see for yourself how quick and easy it is to create meaningful verification plans that the entire project team can participate in.

Written by Team MDV Member
John Brennan

See the MDV Whitepaper on Cadence.com for more information about MDV