Flexible UALink Verification for Any Layer, Interface, and Design Configuration

Modern AI training and inference clusters rely on hundreds or even thousands of GPUs and accelerators working together as a unified compute fabric. As models continue to grow in size and complexity, communication between accelerators has become just as critical as the compute engines themselves.

UALink was created to address this challenge. Designed as a high-bandwidth, low-latency scale-up interconnect, UALink enables efficient accelerator-to-accelerator communication and supports the construction of large AI fabrics where accelerators can exchange data quickly and predictably. Simulation VIP for UALink | Cadence

To achieve the scalability required by modern AI workloads, UALink adopts a layered architecture that cleanly separates protocol, transport, reliability, and physical communication functions. While this layered approach provides significant implementation flexibility, it also creates unique verification challenges. Different projects often implement different portions of the stack, resulting in a wide variety of valid design configurations that must all be verified with equal confidence.

The UALink Layered Architecture

UALink is organized as a four-layer stack:

Each layer serves a distinct function, from protocol transactions at UPLI to reliable transport, replay handling, and physical communication at the lower layers.

Because development often progresses layer by layer, customers rarely verify a complete stack from day one. Depending on project needs, verification may target individual layers, partial-stack implementations, full-stack designs, or custom partitions.

As a result, verification environments must accommodate a variety of implementation boundaries and DUT to efficiently support the full development lifecycle of a UALink design.

Why Layered Protocols Need Layer-Aware Verification

The complexity of UALink verification is not simply a matter of supporting multiple configurations.

Many of the protocol's most important features span multiple layers.

Consider link error recovery. The physical layer is responsible for detecting and recovering from transmission errors, but the behavior ultimately depends on interactions with neighboring layers.

For example, protocol transactions initiated at UPLI traverse multiple layers before reaching the physical interface, while reliability features such as replay and recovery depend on coordinated behavior across layer boundaries. A protocol-only environment may be sufficient for early bring-up, but full-stack validation is often required to expose latency-dependent and integration-related issues.

Consequently, many of the most challenging bugs appear not within a single layer, but at the boundaries between layers.

Successful verification therefore requires visibility into both protocol-level behavior and lower-level link operations.

Multiple Interfaces, Maximum Flexibility

UPLI Interface

Provides a protocol-level entry point for validating UPLI implementations as well as lower-stack DUTs through realistic protocol traffic generation.

DL-PL Interface

For customers focusing on data-link or physical-layer functionality, the DL-PL interface provides direct access to replay, retry, flow control, error handling, and PHY integration behavior, allowing customers to verify DL (w/o PL) or PL (w/o) centric implementations.

Full-Stack Verification

For integrated designs, a full-stack VIP configuration provides complete end-to-end validation across the entire UALink protocol stack.

One VIP for Every UALink Design Configuration

In addition to standard interfaces, Cadence UALink VIP architecture is flexible enough to support implementation-specific environments and custom integration flows, allowing it to fit naturally into customer verification infrastructures. A key differentiator of the Cadence UALink VIP is its flexibility to adapt to any verification interface. It supports a large number of topologies including but not limited to the ones shown in the figure below:

UALink Verification Topologies 

Cadence UALink VIP (Simulation VIP for UALink | Cadence) is designed to support the entire UALink verification lifecycle, from early layer bring-up to full-stack integration.

The solution includes:

• Complete protocol stack support
• UPLI, DL-PL, and full-stack connectivity
• Protocol compliance checking
• Functional coverage
• Error injection capabilities
• Replay and recovery validation
• Advanced debug visibility
• Support for standard and custom verification topologies

The same VIP infrastructure can therefore be used across protocol-layer, subsystem, PHY, hybrid, and full-stack verification environments.

Conclusion

The flexibility of UALink architecture is one of its greatest strengths. However, that flexibility also means there is no single "typical" UALink implementation. Customers may be verifying protocol-layer functionality, link-level reliability mechanisms, standalone PHY implementations, full-stack designs, or any combination in between.

Cadence UALink VIP (Simulation VIP for UALink | Cadence) is built for exactly this reality.

With support for all UALink layers, standard interfaces such as UPLI and DL-PL, full-stack verification capabilities, and the flexibility to adapt to customer-specific architectures, the VIP enables verification across virtually any UALink topology. 

For any clarification or technical assistance, please reach out to us at talk_to_vip_expert@cadence.com. 

Learn more about Cadence VIP on the Cadence VIP website.