Forte and Cadence at DAC: How to Deploy High-Level Synthesis

It's no secret that the transition to high-level synthesis (HLS) has historically gone more slowly than expected. There were a number of reasons for this - the early tools could not successfully synthesize control logic, they could not match the quality of results of handwritten RTL, and there was no standard input language or subset that could be used to build a full design and verification methodology. These issues have been resolved with the introduction of the latest generation of HLS tools.

At Cadence and Forte we have been working with major customers throughout the world to transition their production methodologies from RTL-driven design and verification up to SystemC-driven design and verification. As expected, a lot of this happened first in Japan, but recent years has seen rapid expansion into the other regions, especially Asia-Pacific and some of the major North America-based semiconductor companies.

While we are competitors, we agree on more than we disagree on. We agree that there are huge productivity gains to be had by moving up the abstraction level of design and verification, as well as benefits of broader micro-architecture exploration and easier re-use. We agree that SystemC is the best language for this abstraction level because it is built on C/C++ but adds hardware-specific constructs. We agree about the profile and skill set required to adopt this methodology. We agree that in order to make this transition, it must augment existing methodologies. And we agree on the best way to transition to and proliferate this new methodology extension within a company. Of course one of our major disagreements is who has the better HLS tool.

We have read and heard about so many reports of new IP design requiring armies of engineers and months or years to complete, causing outsourcing of new IP development. Meanwhile we have been working with customers -- especially customers with no legacy methodology to hold them back -- adopt this high-level approach and complete large and complex designs in a fraction of the time with comparable or better QoR. So we thought that it would be useful to share our experiences -- at least on those areas where we agree - with the DAC audience.

This is an audio recording of our DAC 2013 Cadence Theater presentation with slides. Mike Meredith and Mark Warren each lead our field deployment efforts and do an excellent job of concisely summarizing these topics while lending their unique perspectives. Hopefully you find this useful and we can discuss in more detail in follow-up meetings.

The full list of recorded Cadence DAC Theater presentations is here: http://www.cadence.com/dac2013/Pages/theater.aspx

Brett Cline, Forte Design Systems

Jack Erickson, Cadence Design Systems