Free Webinar Thursday 10/13 -- Automating Assertion Generation for Simulation, Formal and Emulation

5 Oct 2011 • 1 minute read

Everyone can agree that Assertion-Based Verification (ABV) is a powerful methodology for uncovering corner-case bugs, exposing functional coverage holes, and increasing verification observability. HOWEVER, there is often one teeny-tiny issue that inhibits its wider adoption: hand-writing assertions can be a real pain. To overcome this obstacle, assertion synthesis technology has emerged that enables rapid proliferation of ABV by automating the painful process of creating meaningful white-box assertions and functional coverage properties with sufficient capacity to handle complex SoC designs. Without writing any additional code, this technology can help you find additional bugs and improve functional coverage, integrating into your metric-driven verification (MDV) flow.

Great stuff -- but how does it work in reality? In a free webinar this coming Thursday October 13, 2011 at 9am Pacific, Team Verify partners with our friends at NextOp Software to show how assertion synthesis works in the real world. In addition to a live demo to reinforce the concepts introduced, we'll review in detail recent case studies from customer projects.

... and see you on the radio soon!

Team Verify and NextOp

P.S. Curious about the technical presenter, Yuan Lu of NextOp? As the CTO of a smokin' hot EDA company, he is great at dividing his time between internal development and meeting with customers. Hence, I suspect webinar attendees will recognize his voice from industry events like DAC and DVCon. For example, here is an interview that Team Verify's editor Joe Hupcey III did with Yuan back at DVCon:

If the video fails to play, click here.

A full blog post on this interview is available here.