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SystemVerilog
debug
Functional Verification
simvision
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IES

FSM Mnemonics Maps (Enums) in SimVision Using Verilog 1364

23 Jul 2009 • 1 minute read

Strong FSM

The mighty FSM – you first learned it when you were a young pup at University (some of you still are!) and you use it day in and day out today.   Such a simple concept – I’m in a known state and I will either remain here or move to a new state based on inputs – but a difficult one to debug when we scale the number of states, number of inputs, and consider asynchronous events.  While we have lots of tools in our belt to verify the FSM including formal analysis and code/functional coverage, tracing the changing states through time in debug is the most commonly used.

Luckily for us, SimVision has the ability to map mnemonics to values in the waveform window to make it easier to visualize the states of the FSM.  The process to do so starts within your IEEE 1364 Verilog code where you’ll need to code parameter or localparam objects that enumerate the state.  Once you have that, you can run the TCL script created and documented by one of our genIES (SimVision and Create FSM Mnemonic maps in SimVision).  An example of how to code the FSM using localparam is shown below:

 

reg [1:0] curr_state, next_state;
localparam EMPTY = 2'b00, INUSE = 2'b01, FULL = 2'b10, ILLEGAL = 2'b11;

 

If you code your FSM using SystemVerilog enumerations, then SimVision will automatically show the correct mnemonics in the waveforms and source annotations:

 

typedef enum bit  [1:0] { EMPTY, INUSE, FULL, ILLEGAL } mystate;
mystate curr_state, next_state;

 

This handy script is provided "as is" for your use and we have other similar "plug-ins" that we will blog on in the future.  If you are thinking "it would be great to automate..." comment on this blog or send us an email at genIES@cadence.com .  Of course, if you do use this tip please comment.  Positive feedback is a magical motivator. :-)

 

=Team genIES

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