GDDR7: Highlights of Memory of Choice for Graphics and High Bandwidth Apps

Graphics Double Data Rate 7 (GDDR7) Synchronous Graphics Random Access Memory (SGRAM) is the latest generation of the Graphics DDR memory that is used in applications like graphics cards, high compute data centers. GDDR devices are also increasingly being used in artificial intelligence (AI) accelerators where bandwidth and performance are key requirements.

This blog talks about the key features of the GDDR7 device standard, the latest version of which, JESD239F, was released by JEDEC in August 2026.

GDDR7-Based System Architecture

GDDR7 SGRAM devices support densities of 16GB through 128GB range with the 266-ball BGA package. A GDDR7 device memory subsystem typically contains four fully independent byte-wide channels. Each channel has its own point-to-point command/address, data, error, and read-clock interfaces. A channel contains 16 banks256-bit internal array access, and a 32n. The normal physical organization can be configured at reset as either four active channels or two active channels. In 2-channel mode, channels B and D are inactive, and their high-speed signals remain High-Z; this enables clamshell PCB topologies using channels A and C from devices mounted on opposite sides of the board.

Device Feature Overview

Channel Operation

Each active channel uses a differential WCK_t/WCK_c input for command/address capture, write-data capture, and read-data timing generation. Internally, CK4 is WCK divided by four and is the reference for cycle-based latencies and command timing. Commands that span more than one CK4 cycle use the last CK4 cycle as the timing reference. The output RCK_t/RCK_c read clock is edge-aligned with read data and may be differential or single-ended, always on, started by a read, started explicitly with RCKSTRT, or disabled.

The command/address interface is packetized over five single-ended NRZ inputs, CA[4:0]. CA[2:0] forms a semi-independent row-command path, and CA[4:3] forms a column-command path. This allows row and column commands to overlap when command legality and all timing constraints are satisfied. The protocol supports single- and multi-CK4-cycle commands, with separate NOP encodings for ordinary command slots and transition sequences.

Data Interface, PAM3 Encoding, and Signaling

GDDR7 supports two data modes. PAM3 is the high-bandwidth mode and uses DQ[9:0] plus DQE. NRZ is the lower-speed, lower-power mode and uses DQ[7:0] plus DQE; DQ[9:8] are disabled. Both modes transfer a 256-bit user payload per channel access. A burst is 16 PAM3 symbols or 32 NRZ bits.

PAM3 Mode

PAM3 represents each unit interval with one of three levels: +1, 0, or -1. With nominal 1.2 V VDDQ, the nominal signaling levels correspond to 100%, 75%, and 50% of VDDQ. Internally, the trits use two-bit representations: 11 for +1, 01 for 0, and 00 for -1; 10 is invalid. At an illustrative 7 GHz WCK, data operates at 14 Gbaud per pin, equivalent to 28 Gb/s over each effective binary data lane and 28 GB/s per channel.

A complete PAM3 burst contains 176 symbols across 11 physical data signals. The data and metadata are packed through several codecs like 11b7S, 3b2S, 2b1S, etc.

Command, Clock, and Configuration Model

The CA interface is SDR relative to WCK and packetizes commands over CA[4:0]. GDDR7 separates an 11-bit row-command path on CA[2:0] from a 7-bit column-command path on CA[4:3], allowing compatible row and column commands to be issued in parallel. Core operations include ACT, RD/RDA, WR/WRA, PREpb/PREab, REFab/REFpb, RFM, MRS, IRD, power-state commands, and training commands.

CABI limits low-going CA activity to reduce command-bus power. CAPAR supplies even parity across the command packet. With CAPARBLK, commands are held until parity is validated; a parity failure blocks execution and drives recovery into CA training with self-refresh. CSP aligns the internal CK4 phase to the host’s four-UI command boundary after CA-training or sleep exit. Optional CSP feedback on ERR lets the controller confirm that CSP was captured before normal traffic resumes.

Sixty-four mode-register addresses are available. MR0–MR47 are standardized or reserved; MR48–MR63 are vendor-specific. Key controls cover PAM3/NRZ selection, read/write CRC, poison, and severity, RL/WL, RCK behavior, termination and driver strength, voltage references, CTLE/DFE/TX equalization, refresh management, training patterns, ECC test, and hPPR. MR10–MR15 are frequency-dependent registers whose updates can be deferred until a sleep transition.

Data Integrity, Electrical Limits, Package, and Implementation Guidance

GDDR7 layers protection mechanisms across command, link, data path, and array:

• CRC: Separate read and write link CRCs use two interleaved CRC-9 engines with polynomial 0x14B over even and odd 164-bit groups, producing 18 checksum bits. The scheme detects all single-, double-, and triple-bit errors, about 99.95% of four-bit errors, and about 99.99% of random burst errors. Write CRC failures are reported on ERR.
• On-die ECC: Minimum capability per 256-bit access is 100% single-bit correction, 100% double-bit detection, and an average 99.3% detection for errors of three or more bits. Corrected data is returned on reads, but ordinary reads don’t scrub the array. Severity metadata reports uncorrectable errors.
• Auto ECS: Background Error Check and Scrub reads codewords, corrects correctable errors, writes corrected codewords back, and logs correctable/uncorrectable events. It operates in REFab(TR=L), Self Refresh(TR=L), or Self Refresh Sleep when enabled. The required average ECS interval tightens with channel density, from 5.15 ms at 4 Gb/channel to 0.64 ms at 32 Gb/channel for a 24-hour full sweep.
• Poison: The host marks a 256-bit packet as known bad; the status is stored under ECC protection and returned on reads. Severity overrides poison when both occur.
• CAPAR/CAPARBLK: Even parity covers the full 20-bit CA packet after CABI processing. Without blocking, a parity error is reported, but the decoded command still executes. With CAPARBLK, the bad command and its paired row/column command are suppressed, subsequent commands are blocked, and the device completes internal work before automatically entering CA Training with Self Refresh.
• ERR: A PAM3 output in both data modes. +1 means no error, 0 reports WRCRC/DPP parity or optional severity, and -1 reports CAPAR, which has priority.
• DPP: Optional end-to-end internal Data Path Protection adds parity across regions between on-die ECC and link CRC coverage.
• hPPR: Permanent row repair protected by a four-command MR31 guard key. The controller must verify spare availability, idle all channels, stop RCK, program at 200–2000 MHz, allow a 2s programming interval, reset, and verify the repaired row.
• CSP feedback: Optional CSP Feedback acknowledges the CSP command after exiting sleep mode, self-refresh sleep mode, or CA bus training. The feedback is transferred to the host by an ERR signal, informs it whether the CSP was properly detected, and whether it is safe to continue with normal operation.

Nominal 1.2 V operation specifies VDD and VDDQ of 1.164–1.236 V and VPP of 1.746–1.908 V. An optional 1.1 V range uses 1.067–1.133 V for VDD/VDDQ. Absolute maxima are -0.3 to 1.5 V for VDD/VDDQ and -0.3 to 2.3 V for VPP. HBM and CDM minimum ESD targets are 1000 V and 250 V. GDDR7 relies on vendor-specific AC values, and system validation for jitter, channel loss, supply noise, and timing margin.

Cadence VIPs offers a comprehensive memory subsystem solution that includes memory models for all generations of Graphics DDR devices (with GDDR7 being the latest), compliant to JEDEC specifications defined for each of those devices, DFI Memory Controller/PHY VIPs and a System Performance Analyzer (SPA) for GDDR devices.

If you have any queries, feel free to contact us at talk_to_vip_expert@cadence.com

More information on Cadence GDDR7 VIP is available at Cadence VIP Memory Models Website.