High-Bandwidth Memory Evolution from First-Generation HBM to the Latest HBM4

HBM4 is the latest generation of the High Bandwidth Memory (HBM) that has become analogous to the artificial intelligence (AI) boom that is everywhere in today’s world. HBM is also increasingly being used in other applications like data centers, autonomous driving systems, servers, and cloud computing, just to mention a few domains where bandwidth and performance are key requirements.

HBM History

HBM started as an answer to the requirement of higher-width GDDR memory devices, which can help with the higher bandwidth and performance needs while keeping the core device architecture still a DRAM with deterministic latency for Read/Write accesses. This new family of DRAMs was designed to work closely with GPUs that are used for graphics and other compute-intensive tasks. The first HBM device standard, JESD235, was published by JEDEC in October 2013.

HBM4

HBM4 is the latest generation of device standard for HBM devices. HBM4 devices have improved on several major features as compared to the previous generation of HBM devices. Some of the important changes are listed below:

I/O and DRAM Core Voltage

HBM4 core DRAM voltage has been reduced to 1.05V, with I/O voltage left to vendors to decide. This is a significant improvement over the 1.1V needed for both the DRAM core and I/O for previous-generation HBM3 devices. This helps with better power efficiency for HBM4 devices.

Channels

HBM4 supports upto 32 channels, which is double the number of channels that was possible with HBM3. This is important performance improvement as the number of core per CPU/GPU has gone up.

Directed Refresh Management (DRFM)

HBM4 devices enhance the DRAM capabilities to keep track of the potential data integrity issues by tracking row addresses, which can then be used by the host to send directed refresh management commands, thus avoiding potential loss of data arising out of row hammering or other similar attacks. DRFM provides additional flexibility to host and can be used independently of the traditional Refresh Management (RFM) and Adaptive Refresh Management (ARFM), which was also supported by HBM3.

WSO Remapping

Traditionally, HBM devices support the repairs of the broken address and data bus lanes by providing a redundant lane, which can be used to remap via both soft or hard lane repair operations. This has been used to improve the assembly yield. HBM4 devices support a new type of option to do WSO remapping that does not operate on an individual channel. This feature allows for post packaging repair of any potential issues with WSO bus lanes themselves, with two additional redundant lanes for the whole IEEE1500 interface.

Decision Feedback Equalizer (DFE)

HBM4 supports the decision feedback equalizer. However, it’s left up to vendors to define the step sizes used for each of the DFE taps.

Mode Registers

As the number of DRAM features increases, HBM4 devices support MR0-MR19, which are four more than what HBM3 had. These additional mode registers are used for features like DFE, DRFM, etc.

The t summarizes the various aspects of HBM devices across generations:

Cadence's comprehensive VIP solution for HBM includes memory models for all generations of HBM devices (with HBM4 being the latest) that are compatible with the JEDEC specification defined for each of those devices, a DFI memory controller/PHY VIP, and a System Performance Analyzer (SPA) for HBM devices. Cadence's HBM4 PHY and controller have been verified with Cadence VIP and are also available as a complete HBM4 memory IP subsystem.

More information on Cadence HBM4 VIP is available at the Cadence VIP memory models website, or if you have any queries, feel free to contact us at talk_to_vip_expert@cadence.com.