How to Maximize Productivity and Lower Cost for Enterprise Prototyping

Semiconductor chips are often produced as application-specific integrated circuits (ASICs) for high-volume electronic devices. It is critical to ensure high quality to avoid the added costs of finding and fixing bugs and remanufacturing the ASIC chip. An unplanned respin can delay the introduction of a product to the market and add tremendous costs in terms of lost business. Design correction and re-fabrication costs are very high. Surveys show that each respin can cost around $25 million for advanced design nodes. This estimate can vary depending on various factors, such as the chip size, mask usage, and the manufacturing node.

Field programmable gate array (FPGA)-based ASIC prototypes are functionally equivalent models of an ASIC design mapped into one or more FPGAs. Prototyping platforms have become essential for early firmware and software development, especially when compounding testing requirements come with increased design size, software content, input data, and workloads to run. However, traditional prototyping solutions require a long bring-up time, especially for large SoC designs. This is because of design re-modification, P&R timing closure, and limited debug capability. The increasing complexity in prototyping has increased costs in hardware, tools, and engineering talent.

Traditional prototyping cost

The complexity of transforming the design across the platforms makes FPGA-based prototyping challenging. With increasing design size, the challenges multiply as the hardware must also scale up. Today’s largest ASICs need hundreds of FPGAs to prototype them. Building such a massive system is a vast and expensive undertaking. Mapping the ASIC design into an FPGA-based platform makes the task further strenuous. When building a prototype, the raw costs of the boards, FPGAs, and other components are minor compared to the expensive engineering project to create a hardware system. Building a sizeable FPGA-based prototype system could take up to a year or more.

The cost of building a traditional prototyping platform is high in both schedule and engineering resources. While ASICs and FPGAs are both types of digital chips, their underlying technologies differ. Elements in the ASIC that do not map directly to an FPGA will have to be changed in the ASIC source code. The expertise necessary to determine the architectural changes to make in the ASIC while keeping enough value in the ASIC prototype for testing requires deep knowledge of the system, architecture, chip design, and verification.

Off-the-shelf boards have additional problems to resolve. Board providers typically provide only minimum software and rely on FPGA vendors for basic functionality such as place and route. However, FPGA vendors do not support multi-FPGA prototypes directly; for example, users must take care of design partitioning across multiple FPGAs. Apart from resolving these issues, you must verify that the design is functionally equivalent to the original and ensure the flow is robust enough to deal with ASIC RTL updates. A lack of expertise in building the flow can spike cost and effort. The manual iterative debugging process involved with bring-up is time-consuming and risky due to limited debug visibility, adding to scheduling costs and engineering resources. This makes build-your-own prototypes no longer feasible for many projects.

Enterprise prototyping is a holistic system-level view of prototyping that addresses all the key areas to increase productivity and reduce costs. Enterprise prototyping includes the hardware for multi-FPGA prototyping and the software to implement an ASIC design into the hardware. Prototypes have evolved to run faster than emulators, differentiating prototyping from hardware emulation.

Using emulators and prototypes in conjunction capitalizes on their strengths. With their faster compile time, emulators help quickly mature the RTL, leading to faster prototype development to find bugs under more exhaustive testing. The emulator can then analyze the bugs utilizing its extensive debug visibility. Combining emulation and prototyping becomes even more potent if they are made to run the same way. Functional congruency of the emulation and prototype model is a requirement. To save debugging time, the emulator and prototype must behave identically. The key elements that go into an enterprise prototyping system are as follows:

• Scalable hardware system that works with both small and large designs
• Software to utilize the hardware
• Library of standard interfaces for hardware and virtual formats

The prototyping system should be tightly paired with an emulation system to enable fast bring-up times and expand debug visibility. When you package these features and capabilities, enterprise prototyping lowers costs through improved productivity, fast bring-up, and quick work performance. 

Protium X2 is the latest generation of FPGA prototyping platform from Cadence. It is an excellent example of an enterprise prototyping system with scalable hardware, a full software stack for design mapping, and a library of hardware and virtual interfaces. Protium X2’s rack-based design is ready for use in a data center or lab environment. It is meant to work with the most significant ASICs or for the centralized deployment of many small ASICs and design prototypes.

When connected to your organization’s network, Protium X2 becomes accessible across geographies. Protium X2 allows your team to work on different designs or run the same ones in parallel. Having one system that caters to all design sizes can save high costs. The cost of setting up and administrating the hardware is often ignored. Centralizing the prototyping hardware takes fewer people to support multiple users and jobs and reduces setup and admin costs.

Bringing up a new prototype typically takes many iterations to find and fix all the issues. The faster turnaround time of a software flow enables engineers to focus on debugging real design issues.

 Faster bring-up with Protium

This chart highlights the time saved during bring-up for different ASIC types and sizes when using Protium software. Protium can bring up the design as fast as two to three weeks, while traditional prototyping can take many months.

Protium software is not just about automating steps but also optimizing the flow for fast turnaround with high-quality results. Traditional prototyping lacks an integrated software flow, so little optimization is possible. Traditional prototyping is often tailored to a specific RTL design and version and needs continuous manual adjustments.

Protium compilation flow

Protium software takes a fraction of the time to run compared to a traditional, manually guided flow. Protium takes ASIC RTL and maps it to the FPGAs with little or no modifications. Protium X2 delivers the right tradeoff to realize a working prototype quickly and run at high speed. The performance is 3X to 5X faster than emulation, fast enough for firmware and early software development.

There are two fundamental aspects to consider in a prototyping platform: scalability and interfaces. Protium X2 scales from ASICs with millions of gates to multi-billion gate designs. With its rack-based architecture, Protium X2 maintains performance with the most effective designs. The interfaces to the enterprise prototyping system are as important as raw capacity and speed. Interfaces such as IO adapters, speed bridges, virtual interfaces, and hybrid models connect the prototype to the environment and use models that make the prototype work. A complete enterprise prototyping system must have all these interfaces ready to use and tested rather than leaving it to the user to develop them. Protium X2 delivers the complete package.

 Regression acceleration, software, and system validation with virtual and ICE devices

Protium’s breadth of interconnect solutions enable all common-use models for FPGA-based prototypes. It enables in-circuit emulation through hardware interfaces connecting you to standard customer devices and test equipment. AVIPs allow a virtual extension of hardware interfaces into the software world for hardware regressions and software-driven test environments. Virtual bridges and hybrid models enable a much richer software development environment that boosts software developers’ productivity.

Cadence has partnered with leading CPU debug tool providers to connect to Protium through physical and virtual interfaces. Providing easy access to software development helps improve software and hardware quality. Enterprise prototyping thus enhances productivity and reduces costs beyond the delivery of just the prototype. Using an enterprise prototyping system is a much more cost-effective approach to creating an FPGA-based prototype than traditional prototyping. Protium X2 ticks all the boxes for platform completeness—fast time to prototype and work performance and efficiency.

This blog is an excerpt from the CadenceTECHTALK: Protium Enterprise Prototyping: Higher Productivity, Lower Costs by Lance Tamura, Product Management Director—watch this on-demand webinar.