How to Maximize Your Verification Experience at DAC 2016

2 Jun 2016 • 13 minute read

Next week will mark the annual EDA gathering in Austin. For me it is my 20^th DAC … I know, compared to some I am still wet behind my ears, but that’s only because I started my career in embedded software and actual chip development. I already outlined in my Blog “The Top Five Trends In Verification To Watch For At DAC 2016”.

The System Development Suite is all about the connection between different engines and the verification fabric holding them together, maximizing throughput, allowing you to get to sign-off in a metric driven fashion and doing it an application optimized fashion.

Here are the events to attend to maximize you verification related experience at DAC:

Personally I am looking forward to the lunch panel we organized - Jim Hogan's insights are always fun and he will introduce the challenges. Insights from AMD, NVIDIA and Cadence will be invaluable when it comes to the verification fabric, hardware assisted verification and portable stimulus. The panel I am on at 3:00pm at the ChipEstimate booth promises to be entertaining as well.

Monday, June 6^th 2016	Cadence DAC Theatre, Cadence Booth, #107
	Time	Company		Title
	10:00am	Rocketick		Introducing RocketSim™: the Fastest Digital Simulator
	11:00am	ARM		The ARM® Universe of Models and Its Interoperability with Cadence® Verification Flows
	4:30pm	Cadence		Comprehensive SoC Standard Interface Verification
	Panels
	Time		Company		Title
	12:00pm		Cadence ARM AMD NVIDIA Vista Ventures		Seamlessly Connected Verification Engines? What Does It Take? Ballrooms B/C Alex Starr - Advanced Micro Devices, Inc., Boxborough, MA Narendra Konda – NVIDIA, Santa Clara, CA Mike Stellfox - Cadence Design Systems, Inc., San Jose, CA Jim Hogan – Vista Ventures, San Jose, CA Moderated by Brian Fuller, ARM
	3:00pm		ARM Cadence National Instruments		How Can New Start-Ups Build the Next Great IoT Chip? ChipEstimate Booth Nandan Nayampally, ARM Frank Schirrmeister, Cadence George Zafiropoulos, National Instruments Moderated by John Blyler
	DAC Tutorial, Room 15
	1:30pm to 3:30pm	How Portable Stimulus Addresses Key Verification, Test Reuse, and Portability Challenges
	Expert Bar, Cadence Booth, #107
	Time	Company		Title
	10:30am	Cadence Verification and Implementation Solutions for ARM® Based Designs
	2:30pm	The Future of Verification with System Development Suite Simplify SoC Verification with VIP
	4:00pm	Software-Driven SoC Verification featuring Perspec™ System Verifier
	Verification Experience Room , Cadence Booth, #107
	2:00pm	IP and Sub-system Verification – JasperGold®, Incisive®, VIP and vManager Technologies
	For private meetings, please contact your sales person or email Pam Swarts directly at swarts@cadence.com

For Tuesday keep some energy for the later part of the day. Yep, for the Denali Party by Cadence as well, but the afternoon with the "Simulation/Emulation Faceoff promises to be a highlight at 3:30pm. I am looking forward to AMLogics presentation how they apply both Palladium and Protium to their design challenges. The Low-Power panel I am on during Tuesday morning at the SI2 booth will be hot - pun intended. Lots of Portable Stimulus partners are on that day in our Theatre - Vayavya and National Instruments as eco-system partners. Our ecosystem partner Teledyne LeCroy will present on PCIe and Palladium.

Tuesday, June 07, 2016	Cadence DAC Theatre, Cadence Booth
	Time	Company	Presentation Title
	10:00am	AMLogic	Pre-silicon Software Development with Protium™/Palladium® Environments
	1:30pm	ARM	Accelerated System Optimization with CoreLink™ Creator and Interconnect Workbench
	2:00pm	Vayavya Labs	Software-Driven Validation: Using Perspec System Verifier and DDGen
	3:00pm	National Instruments	Portable Stimulus for Verification and Post-Silicon Test – How to Connect These Two Worlds
	4:00pm	Teledyne Lecroy	Ubiquitous PCI Express Verification from Simulation Thru Post-Silicon Development
	Panels
	Time	Company	Title
	11:00	AMD Cadence IBM Broadcom	What's Hot and What's Not in Low Power SI2 Booth #239 Aaron Grenat, AMD Frank Schirrmeister, Cadence Nagu Dhanwada, IBM John Redmond, Broadcom
	3:30pm	AMD Cadence IBM Mentor OneSpin	The Great Simulation/Emulation Faceoff Ballroom E Alex Starr - Advanced Micro Devices, Inc., Boxborough, MA Frank Schirrmeister - Cadence Design Systems, Inc., San Jose, CA Ronny Morad - IBM Research - Haifa, Israel Stephen Bailey - Mentor Graphics Corp., Longmont, CO Dave Kelf - OneSpin Solutions GmbH, San Jose, CA Moderated by John Sanguinetti, Adapt-IP
	Expert Bar, Cadence Booth, #107
	10:00am	Software-Driven SoC Verification featuring Perspec System Verifier
	11:30am	The Future of Verification with System Development Suite Formal Verification Featuring JasperGold® Apps
	1:00pm	System Verification and Hardware/Software Co-Verification with Palladium® Z1 Verification Plan, Coverage, and Debug with Incisive® vManager™ and Indago™ Debug Solutions Cadence Verification and Implementation Solutions for ARM-Based Designs
	2:30pm	High-Performance Simulation with Incisive and RocketSim™ Technologies
	4:00pm	Software Development with Protium™ Rapid Prototyping
	Verification Experience Room , Cadence Booth, #107
	2:00pm	SoC Integration and Verification – RocketSim™ & Incisive®, Palladium® Z1, Interconnect WorkBench, and vManager™ Technologies
	For private meetings, please contact your sales person or email Pam Swarts directly at swarts@cadence.com

Wednesday will be dominated by portable stimulus - MicroSemi as user, Agnisys as partner - as well as software with ST's presentation on Indago embedded software debug.

Wednesday, June 8, 2016	Cadence DAC Theatre, Cadence, Booth, #107
	Time	Company	Title
	10:00am	Adapt-IP	Design and Verification of Flexible 802.11ah Base Band IP Using High-Level Synthesis
	10:30am	Agnisys	Portable Software-Driven Verification
	12:00pm	Microsemi	Evaluation of Perspec System Verifier SW-Driven Test Automation
	12:30pm	Cadence	Accelerating Interface Debugging with Indago Protocol Debug App
	4:00pm	Methods2Business	Innovate in Wi-Fi HaLow IP for IoT with SystemC-based design and Xtensa® DSP Technology
	5:00pm	STMicroelectronics	A Better Approach for Today’s Debug Challenges
	5:30pm	AMD	Emulation Productivity: Beyond the Specs
	Expert Bar, Cadence Booth, #107
	10:00am	System Verification and Hardware/Software Co-Verification with Palladium Z1
	11:30am	Software Development with Protium Rapid Prototyping
	1:00am	High-Performance Simulation with Incisive and RocketSim Technologies
	2:30pm	Formal Verification Featuring JasperGold Apps
	4:00pm	Verification Plan, Coverage, and Debug with Incisive vManager and Indago Debug Solutions
	Verification Experience Room , Cadence Booth, #107
	2:00pm	Hardware-Software development – Palladium® Z1, Protium™, Joules™, Indago™ and Perspec™ Technologies
	For private meetings, please contact your sales person or email Pam Swarts directly at swarts@cadence.com

See you at DAC!