Never miss a story from Verification. Subscribe for in-depth analysis and articles.
High-end SOC architectures today requiring more area and higher speed to transfer and process data. To fulfill this requirement, protocol such as PCIe, USB, DP, SATA and USB4 are regularly being updated. Most critical part of the high-speed interface is the Physical (PHY) layer of the protocol where the actual signaling happens. In addition to signaling, the PHY also takes care of some of the processing to reduce errors in transmission and error recovery. This makes the PHY design very complex as it involves both high speed digital logic and analog circuitry. Usually the rest of the protocol can be implemented purely using digital logic. Hence the IP/SoC developers develop the PHY separately from the rest of the protocol logic. This will allow both developments to happen in parallel and independently. This created a need for a standard interface between PHY module and rest of the protocol logic. The PIPE specification effectively defines this interface. One of the intents of the PIPE specification is to accelerate the development of PCIe, SATA, USB, USB4, DP MAC. The most recent changes in the PIPE is SerDes architecture and low pin count interface. The PIPE specification has upgraded to version 6.1.1 to match the latest protocol specifications of PCIe, DP and USB4.
Also, the aim of the PIPE specification is to make possible one universal PHY that can be used across protocols such as PCIe, DP and USB. This means it will be good to avoid protocol specific logic in PHY. Earlier PHYs contained some of the scrambling logic, encoding/decoding logic within the PHY. This meant that PHY had to know the protocol that it was working with. From PIPE 5.x onwards, all this logic was moved to MAC and PHY performs bare minimum functions such as serialization/deserialization, bit lock, and clock data recovery.
Most of the non-time/speed critical signals are moved to the message bus from PIPE version 5.x onwards to achieve higher functionality with low pin count and thus not add to the chip cost. This approach is scalable for future protocol enhancements. This simplifies the PHY design and allows it to be shared easily by different protocol stacks. Cadence has developed a VIP solution to specifically verify standalone PHY DUT design. Our PHY solution supports SerDes architecture and original architecture and all the versions of PIPE starting from version 4.3 to 6.1.1.
This solution consists of three components PIPEXceiver, SerialXceiver, and PHY monitor. PIPEXceiver and SerialXceiver components were developed to be able to drive and receive traffic to/from PHY DUT. These components provide very granular control of all PIPE interface signals. PHY monitor was developed to monitor the serial and parallel interfaces of the PHY DUT and-, check data integrity across the PHY DUT.
Verification Block Diagram of PHY design
Cadence has developed a Full stack VIP solution where we can use Protocol VIP like PCIe, USB3, and USB4 to verify PHY DUT. Cadence has enhanced above verification environment where we can have protocol VIPs to verify PHY DUT. Protocol VIP connection with PHY VIP is under the hood and transparent to the end user. There is no signal interface connection between Protocol VIP and PHY VIP components. This way user can ensure that PHY DUT is verified thoroughly with real protocol traffic.
Verification Block Diagram of PHY design using Protocol VIP
For more information on Cadence PHY Verification IP, see Simulation VIP for PIPE PHY, and for more details on simulation VIP like PCIe, USB3, or USB4, you can refer to the Simulation VIP website.