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Applications like Automotive, Industrial control panels, Smart Home, Smart watches, smart speakers and bends require Low cost, Low power consumption, High computing efficiency, Easy to control and Low form factor memory devices to process data temporarily to gain widespread adoption in the market place. HyperRam memory has all above characteristics to improve performance of end devices.
The HyperRam device is the high-speed CMOS, Self-Refresh Dynamic RAM (DRAM) which uses HyperBus Interface. Since, the Host doesn’t require to manage any refresh, the DRAM array appears to the host as static cells that retain data without refresh. Hence memory can also be described as Pseudo Static Ram (PSRAM).
Benefits of HyperRam
HyperRam has only 13 signal I/O pins, which means that, when designing end products, MCU have more pinouts for other purposes, or it allows you to use MCUs with small form-factor for better cost-effectiveness. HyperRam has fewest pins to achieve approximately the same throughput (333MB/s), compared to similar DRAM—like LPDRAM, SDRAM etc.
When Hyperram device is not required for system operation, it can be either placed into Hybrid Sleep mode in case data need to retain for partial power saving or it can be placed into Deep Power Down mode to achieve maximum power efficiency.
Hyperram devices include self-refresh logic that will refresh rows automatically thus controller design will be less complex.
Cadence has a Memory Vendor Program (MVP) in place with HyperRam Memory vendors like Cypress and Winbond, thus Cadence has early access to their Datasheets to develop HyperRam Verification IP (VIP).
With the availability of the Cadence Verification IP for HyperRam, early adopters can start working with specific Memory Vendor Datasheets immediately, ensuring compliance with the vendor standards and achieving the fastest path to IP and SoC verification closure.
More information on Cadence HyperRam VIP is available at Cadence VIP Memory Models Website.