Informative Tweets on WHEN Inheritance

4 May 2010 • 3 minute read

Earlier today a lively and very instructive thread on the relative virtues of WHEN Inheritance developed on Twitter between @pmarriott (a D&V consultant in Montreal, Canada), @yaron_think_ver (a verification consultant based in Israel), and @teamspecman.

Because this exchange was very technical -- hence, beneficial to Specmaniacs -- for those of you not yet on Twitter allow us to replicate the thread here, plus address some of the questions / issues raised that we haven't yet responded too (because we must confess, the the 140 character tweet size limit gets a little tiresome after awhile).

By all means we invite @pmarriott, @yaron_think_ver, and YOU to continue the discussion on Twitter by following the three of us and start tweeting youself, or post comment(s) below.

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Initial entry by @teamspecman, 5/3 14:00

Q: Can you replicate e's 'when' inheritance in SystemVerilog? A: Not really. TSN's Corey explains in the comments: http://bit.ly/agcymd #EDA

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Comment by @pmarriott, 5/3, 14:54

@teamspecman isn't "when" inheritance was only useful for data items? The OVM/sequences+factory+polymorph makes it redundant anyway surely?

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@teamspecman (3 tweets in a row), 5/4, 10:22, 10:23, 10:24

Untrue. There R many aspects that can be added to environment objects such as RT @pmarriott isn't "when" inherit only useful for data items?

Part2: Checking, coverage, speed rates, etc. can all be modeled through 'when' inheritance. Plus ...

Part3: Toggling UVC agents from ACTIVE or PASSIVE in an OVM e env is modeled very elegantly using 'when' inheritance

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@pmarriott, 10:25

@teamspecman those env objects are static at run time so when inheritance is less useful - can use regular OOP/factory for their morphology

--> new, Team Specman long form response to this tweet:
They are static at run time however, the topology of an environment can change. Consider the bus speeds to drive at, the bus widths to drive data across, the configuration of the environment, how many channels are active in the environment, how many DUT's are present in some sort of chain configuration, whether or not you are running in 40G vs 10G operation mode, and the list goes on and on. If all of the above parameters needed to be tested (IP developer situation), using child classes and factories to configure the environment in every possible mode is extremely tedious to do. Why not let the Generation engine do this for you?

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@pmarriott, 10:30

@teamspecman setting a status bit through an accessor method will achieve ACTIVE/PASSIVE toggling too. "when" fields R like case statements

--> new, Team Specman long form response:
We're not sure we understand what you mean by "accessory method". However, we are sure that you could model the ACTIVE/PASSIVE functionality in a number of ways. It is the beauty of AOP though that allows users to extend objects based on whether they are ACTIVE or PASSIVE. Consider adding a new debug statement to be printed out at the end of some sort of transfer reception only on the ACTIVE monitor driving input channel 3. This is easily achieved through the following: extend ACTIVE CHANNEL3 agent_u { //place print code here};

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@yaron_think_ver, 10:34

@teamspecman @pmarriott Also, #Specman's WHEN is a cool way to implement multidimensional inheritance. Anything similar in #SystemVerilog?

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@pmarriott, 10:47

@yaron_think_ver @teamspecman "when" does not really give multiple inheritance,though you can do some composition using it, that's different

--> new, Team Specman long form response:
Incorrect: multiple inheritance IS something supported in e through its OOP capabilities. struct b_s like a_s {}; means that b_s will now inherit the properties of a_s. Similarly c_s can inherit from b_s and so forth. What is cool about `when` inheritance though is that one can extend objects based on any number of aspects, allowing you hone in on a very specific subtype such as extend has_checks PASSIVE CHANNEL1 USB30 monitor_u { ...}, which is something unique to e.

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@yaron_think_ver, 10:53

@pmarriott Correct. If you have subtype A and subtype B, you automatically have subtype "AB". Not sure if this is possible in #SystemVerilog

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@yaron_think_ver, 10:56

Can be very useful: define LONG eth_frame, BAD_CRC eth_frame. U can now use these 2 and also LONG BAD eth_frame

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@yaron_think_ver, 11:05

It's not unusual to see things like this in #Specman: var fr = LONG VLAN GOOD_CRC HAS_TCP HAS_IP eth_frame ... not kidding! pretty neat :-)

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@yaron_think_ver, 11:09

Doing the same in #SystemVerilog is definitely possible but would require a bit of procedural coding (if/case in pack/unpack) wouldn't it?

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@pmarriott, 11:27

@yaron_think_ver some of those long "when" composites make for tricky casting, that's for sure. Always looks sexier than the reality of use

Team Specman

(on Twitter: @teamspecman)