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With higher speed introduced from PCIe 5.0, high 32.0 GT/s insertion loss target (-36dB) leads to a higher DFE tap ratio which, in turn, may trigger burst errors due to error propagation following a single bit error. Because of a high DFE tap ratio, if a bit flips and the data is a 01010 pattern, then the bit that flipped influences the DFE the wrong way, so it flips the next bit, which then influences the next bit, and so on... the problem corrects if bits did not alternate since the DFE would settle properly. Burst errors can eventually break the CRC detection capability. They can also lead to SKP Ordered Set corruption
Precoding concept is introduced in PCIe 5.0 Spec and defined new precoding logic for 2-bit aligned UI level (PAM4 used in PCIe 6.0). A Receiver may request precoding from its transmitter for operating at data rates of 32.0 GT/s and higher. Precoding, when enabled at a Data Rate, applies to both Flit Mode and Non-Flit Mode at that data rate.
Precoding used at 64.0 GT/s serves the same purpose as it can help mitigate the number of errors in a burst. The major difference between precoding at 32.0 GT/s and 64.0 GT/s are:
Below schematic shows the 1b/1b Encoding for 64.0GT/s and higher data Rates. When the PCI Express Link is operating at 64.0 GT/s or higher Data Rates, it uses Flit Mode. A Symbol (8 bits) is the basic unit of transfer per Lane. PAM4 signaling is used for all Symbols. At a Flit level, on the Transmit side with per Lane basis, Scrambling is performed, if required, followed by Gray Coding at a 2-bit aligned boundary, after which Precoding is performed at 2-bit aligned UI level, if enabled and required.
The Receive side is similar to the Transmit side in the opposite direction. After the PAM4 voltage is converted to a 2-bit aligned quantity, it undergoes the Receive side precoding if applicable followed by the decoding of the Gray code, followed by descrambling on a single bit level, if applicable.
Figure 1 shows the 1/1+d precoding used in PCIe 6.0.
Let’s look how exactly precoding algorithm works for 64.0GT/s.
At transmit side, only scrambled bits on a 2-bit aligned boundary are precoded, when both bits are scrambled and precoding is enabled. the input is Pn and the output is Tn. Tn−1 represents the output from the precoder in the previous UI. When the prior UI had an unscrambled signal and precoding is enabled, Tn−1 is set to 00b. The output Tn will be converted to the PAM4 voltage levels. The Truth Table for the Precoding function for the Transmit is shown below:
On the Receive side, Rn = Tn + En. The input to the Precoding logic is R′n (Rn = Tn + en), where en is inclusive of the error on the wire En as well as any internal DFE propagated error. The output of the precoding logic is P′n, when precoding is enabled. The Truth Table for the Precoding function for Receive side is shown in above.
As we already discussed, precoding can convert continuous multi-bit burst error into 2-bit start error and end error, to achieve the purpose of eliminating burst error. But for a single-bit error, it will become a 2-bit error after precoding is turned on, so that the system bit error rate BER will be doubled.
From below figure, we can see when the bit stream on the link is continuously flipped over multiple bits (Left), after the actual receiving end passes through the precoding module, the number of flipped bits drops to two. This is why precoding can reduce the impact of burst error.
When we flip one bit in the bit stream (right), after passing through the precoding module at the receiving end, the restored data has two incorrect bits. Therefore, it is said that double BER will occur after precoding is turned on.
In summary, precoding is an important feature introduced in PCIe 5.0 and enhanced to support 2-bit aligned quantities with PAM4 encoding in PCIe 6.0. With the new logic introduced, the chip designer and verification engineer needs to ensure the new algorithm implemented correctly. Cadence’s Verification IP (VIP) for PCIe 6.0 is fully compliant with the latest PCIe 6.0 specifications and provides an effective and efficient way to verify the components interfacing with the PCIe 6.0 interface. Cadence VIP for PCIe 6.0 provides exhaustive verification of PCIe-based IP and SoCs, and we are working with early adopter customers to speed up every verification stage.