iPhone 3G issues - result of HW/SW-co-verification?

In a recent article at cnet, financial analyst said he believes Apple's iPhone 3G reception issues may be the result of some faulty chips. Richard Windsor of Nomura published a research note singling out the iPhone 3G's chipset, made by Infineon, as the probable culprit for the reception problems.

The dropped calls, service interruptions, and abrupt network switches experienced by iPhone 3G users reminded Windsor of similar complaints five years ago, when 3G phones were first launched in Europe. In his quote, Windsor wrote: "we believe that these issues are typical of an immature chipset and radio protocol stack where we are almost certain that Infineon is the 3G supplier.

This is not surprising as the Infineon 3G chipset solution has never really been tested in the hands of users. Some people will not experience these problems as it is only in areas where the radio signal weakens that the immaturity of the stack really shows."

So, do we really want to wait for the end users to test these issues or do we want to do it up-front through our verification process?

Cadence emulators and its Incisive Software eXtensions (ISX) can help you to verify your hardware and software (or artificial SW) together early in the design process. Many recalls and end-users problems can be prevented up-front through the verification process with these capabilities.

If you want to hear from other users and understand how they prevented recalls and HW/SW co-verification issues early in the process, I would suggest you will sign-up for CDNLive in San-Jose in the beginning of September 2008.

1.      During the system-level verification techtorial on September 8th , we are going to demonstrate these capabilities and several users will talk about their experience with these tools and the benefits, they have achieved.

2.      On September 9th, 10th and 11th, key users will have 45 minutes each to present their HW/SW co-verification methodologies and the success they have got. Specifically look at:

·        Track 1 Session 1FV5 – Using ISX to build a constrained random test environment from directed C-based tests.

·        Track 1 Session 1FV6 – An HDTV SoC Development Team’s first Experience with HW/SW Co-Verification

·        Track 2 Session 2FV7 – Maximizing the ROI of Palladium of Palladium HW to validate massively threaded CMT processor

·        Track 1 Session 1FV12 – System-level verification of hard disk controller using Specman and ISX

3.      Come and listen to Cadence System Design and Verification overview and roadmap – Track 1 on september 10th at 4:30pm

4.      Come and see variety of HW/SW co-verification demos on September nigh at the technology night

If you are interested to hear about Cadence system design and verification overview and roadmap, don't miss track 1 Session 1R11 on September 10th at 4:30pm.