ISX Presentations at CDNLive! Munich

As we head into next weeks CDNLive! event in Munich it's great to see today's post in the Industry Insights area by Richard Goering on the Embedded Software Challenge. It provides concrete data on the rising costs of embedded software design and verification for those who have been wondering if I have been crying wolf for what is now approaching one year of blogging. In fact, the article by Richard connects back to my very first post on cadence.com that summarizes the dramatic change that has occurred from the days when I was a Cypress FAE selling chips by dropping off data sheets and asking the sales guy to send some device samples.

I won't be at CDNLive! this year, but I would like to point out two great presentations for those that will be there. Both are on Wednesday, May 20, in the System Design and Verification Track.

The first presentation is SD&V03 titled Reduced verification effort using software/hardware coverification. The presentation starts with an interesting motivation, Reduce Verification Effort. Most engineers assume that incorporating embedded software into a hardware verification project comes with extra effort, requires more communication, involves people with skill gaps, and generally makes life more difficult. While some new skills are needed, the results demonstrate that this extra time to introduce embedded software is negligible compared to the savings realized from leveraging software instead of spending so much time writing testbench code that is duplicating the function the software must do anyway. If you are a verification engineer writing e or SystemVerilog tests to configure a device and program it to perform its function this is be a great presentation to attend.

The second presentation is SD&V06 titled Coverage Driven Verification applied to Embedded Software. The presentation details an automotive application running on a SystemC model of a PowerPC. It provides a good introduction to ISX with useful examples of properties that can be verified using constrained-random stimulus generation, checking, and software monitoring, and how some of these properties can cross the boundary between hardware and software. Comparisons between dynamic verification and tools like the BLAST model checker are also provided.

For those attending, have a great conference, and for those of us stuck at home, we look forward to hearing about the highlights and reading the proceedings.

Jason Andrews