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Asynchronous designs happen. They’re not particularly easy to verify, but sometimes they’re necessary. If you don’t have a system clock, or if you have controllers that operate at a high speed with low power dissipation, or even if you do have a system clock but it’s noisy, your design may be asynchronous, and that’s okay. It’s no secret that asynchronous designs are a challenge—so what can you do to make sure they’re hazard-free?
Enter JasperGold FPV—Cadence’s formal verification tool. With JasperGold FPV, you can catch potential issues in your design far earlier in the design process than ever before.
Hazards in asynchronous designs are trickier to catch than normal, and their impact on the system can be more severe. Normally, if a hazard occurs in a synchronous system and it’s not within a timing window for data capture, it’s not necessarily an issue—however, asynchronous designs don’t have these windows, and as such hazards can’t be occasionally buried in a clock cycle. This—and problems like it—are likely to arise in analog systems and during asynchronous resets.
Now, how does one address these problems? You could do a post-layout SPICE simulation, but that takes a long time, and it’s complicated. You could also do a gate-level simulation, but that also takes a long time, and it’s difficult to debug.
JasperGold FPV is a far better solution than either of these. If there is a combination of logic that results in a glitch, JasperGold FPV will find it. With FPV, delays can be added to each node individually to simulate delay however you like. You can use soft constraints to minimize non-zero delays, and quiet traces can simplify counter-examples. As eloquently explained by Noor Elahi of TI in his recent CadenceLIVE presentation on this subject, these hazards occur because delays in asynchronous designs aren’t predictable—thanks to their lack of consistent clocks—and random differences in the order of signals arrive can cause unexpected behaviors. Formal verification is a great choice for finding these hazards precisely because delays are not accounted for and every possible combination of signal arrivals is explored.
JasperGold FPV is proven to work. In a customer’s design, JasperGold FPV analyzed an asynchronous design with eight states, ten inputs, 40+ gates, 100+ delay arcs, and over 2000 registers in its delay elements, and found bugs that other tools didn’t find. It even found a scenario in an established design—and being able to fix these bugs pre-silicon can make a huge difference in the success of a chip.
So what are you waiting for? Come see what JasperGold FPV can do for you.