Low-Power IC Design: What Is Required for Verification and Debug?

Low-Power Design Techniques Are Needed

In today’s world, energy saving is a hot topic. All kinds of devices are pursuing low-power consumption to be ecofriendly or to lower the operating costs. To address these goals, chip designs today have to chase for not only high performance but also need to be energy efficient. As a result, chip design engineers must ensure their designs consume as less power as possible while maintaining all the required functionalities and keep performance competitive enough in the market. Low-power IC design is obviously a trend today. How to build a chip with low-power techniques becomes very important. This article will discuss what should be considered in low-power designs and how to debug it effectively. 

UPF, Describing the Low-Power Intent

Unified Power Format (UPF) is a widely used language standard for describing low-power design on top of digital circuits. UPF allows designers to specify power management techniques such as power domains, power states, voltage scaling, and clock gating to reduce power consumption. However, applying UPF to design can sometimes be challenging because of the correlation between the design and its complexity.

To verify a design with UPF power intent, the following are some tips and techniques that engineers need to look into:

Analyze the Power Intent

The power intent of the design must be analyzed to ensure that it meets the requirements. It is essential to check whether the power domains are correctly defined and the power modes are appropriately implemented. Moreover, the power states should be verified to ensure that they are consistent with the power intent of the design

Verify Power Switch Connectivity

Power switches are essential components in UPF design as they control the flow of power to the different power domains. Any issue with the connectivity of the power switch can cause the design failure. Therefore, it is essential to verify the connectivity of power switches and ensure they are correctly connected to power domains

Verify the Power State Transitions

The power state transitions of the design should be verified to ensure they are working correctly. Any issue with the power state transition can cause the design to fail, leading to incorrect functionality. Therefore, it is highly recommended to verify the power state transitions and make sure they are functioning as expected.

Check UPF in Static and Dynamic Ways

The tips described above can be categorized into two categories, static and dynamic checks.

Static checks: This refers to the structural check of UPF. For example, the UPF description of power domains and the connectivity. Both do not require to run simulation to validate the behaviors, but engineers need to understand the power domains are properly defined and their connectivity are correct between power domains.

Dynamic checks: Meaning the behavior of design after applying UPF description. Engineers need to verify the correctness of the power state and power sequences. When does the power domain need to turn on, and when does the power domain need to shut down? And the logic sequences when power states are changed. All these behaviors need to be verified through simulation to make sure the behaviors are as expected.

What Is Needed to Solve Challenges from UPF Low Power Design?

From the design engineer’s point of view, it is natural to guarantee the functionalities of designs are correct. However, designs today do not only talk about functions, but low power consumption is also a requirement in the checklist. To achieve low-power (or even ultra low-power) consumption, additional power descriptions are also a required implementation. This is truly increasing verification efforts to the next level.

To help engineers with both design and UPF that is added into the design at the same time, an integrated debug environment becomes very important! It will provide both information on the design and UPF to help engineers comprehend design and power intents easily.

Cadence Verisium Debug now allows users to read in both HDL design and UPF power description. Once design and UPF low-power are imported, an integrated environment allows engineers to analyze the data from both sides.

                                       Figure 1: Power Browser

By combining HDL design hierarchy and UPF power intent hierarchy together, an engineer can easily examine if the power domain lies in the correct design scope and if all the power control signals are described in the right manner.

With the tight integration between Cadence Xcelium simulator and Versium Debug, the result from low power simulation can also be annotated onto the hierarchy and relevant signals. The user can understand what power domains are turned on and what are the values of each power control signal. Also, the simulation results can also help to understand the transitions of power states and sequences. All these can help engineers to understand how the power intents operate and also check if the impact of power transition is correct instead of causing function failures.

Figure 2: Integrated SmartLog with UPF source

The integrated view also allows users to trace not just within HDL source code. Users can also easily trace into UPF source code. The integrated HDL and UPF debug environment provide a seamless capability, which helps engineers debug design and low power easily.

Figure 3: Power Aware Schematic

Another important feature that can really help is the power-aware schematic. When writing UPF code, it’s sometimes very difficult to determine if the definition of power domains or power structure are designed properly, are all the power domain defined, or if all the connectivity is correct. A graphical view really helps engineers visualize this information. Power domain connections and status, all can be visualized on power-aware schematic.

Figure 4. Power Aware Waveform

Last but not least, how do you visualize the result from power-aware simulation? With the tight integration with Xcelium, Verisium Debug can access the additional power related activities from simulation and annotate the low-power events onto the waveform database. Which power domain does this signal belong to? What’s the property of the signal, and is the relevant power turned on? All the needed information can be seen in the same waveform window.

Conclusion: Integration Between Tools and Unified Debug Environment Is the Key

UPF low-power verification and debug involve more than one language and requires more than one EDA tool to work together for low-power implementation or verification. For example, the simulator runs power-aware simulation and generates dynamic data of how it works when applying power intent. It is required to have a debug solution that is integrated with the simulator and can access and provide the required data for visualization and debugging. If the engineer can only see signals from HDL without power-related information, then it will be very difficult to troubleshoot the issues that are impacted by power intents. Furthermore, only a unified environment can provide the most efficient debug solution to debug power-aware designs.

The integration between Xcelium and Verisium Debug guarantees direct access to the design and power-related data that can help engineers visualize the static and dynamic information of low-power designs. Combining both HDL and UPF together is a requirement to have a unified environment to work on low-power design verification and debug.