LPDDR5 Verification from PHY to System Level

Today’s mobile devices come with a 5G network connection, 4K video recording, live streaming, and ever more realistic video games that demand higher performance and lower power processing. Furthermore, as the adoption of ADAS and autonomous technologies rapidly increases, data capture and efficient processing are becoming key to automotive innovation. 

High-performance is achieved with a high-performance processor taking to high-performance memory. Low power requires low-power memory coupled with a power-optimized memory interface. While the bandwidth of LPDDR4x is maxed out, LPDDR5 enhances the speed of operations and comes to the rescue. It is designed to speed up performance, improve signal integrity, reduce refresh times, and satisfy the performance and memory density demands of the latest generation of mobile devices such as smartphones, tablets, ultra-thin notebooks, and similar connected devices on the newest, high-speed 5G networks, and automotive.

LPDDR5’s energy efficiency enables high-performance compute for cars while minimizing power consumption for both electric and conventional vehicles, resulting in greener transportation with lower emissions.

LPDDR5 is the next-generation low-power memory which boosts 1.5X faster data transfers than its predecessor, LPDDR4. LPDDR5 devices can transfer data at rates as high as 6400Mbs with remarkable power efficiency. It also supports a unique low power feature and deep sleep mode (DSM), to reduce standby power even further.

These capabilities equip intelligent vehicles with near-instantaneous decision-making from the fusion of multiple sensors and inputs, such as radar, lidar, hi-resolution imaging, 5G networking, and optical image recognition.

We get different verification challenges as we move to different levels from PHY to IP to the SoC integration level. In this blog, I will be discussing how Cadence can help overcome the LPDDR5 verification challenges, from checking the specification compliancy of your IP design to integration and performance measurement when moving to System-level.

PHY Level Verification Challenges                                                

• Timing Violations
• Low-level Testing
• Error Injection
• DFI 5.0/5.1 compliance Spec assurance
• LPDDR5 compliance Spec Assurance
• Multiple configuration Testing
• DFI and LPDDR5 Interface data integrity matching

IP Level Verification Challenges

• Timing Violations
• DFI 5.0/5.1 compliance Spec assurance
• LPDDR5 compliance Spec Assurance
• Multiple configuration Testing
• LPDDR Vendor Specific part number testing
• Easy protocol level debugging

SoC Level Verification Challenges

• Integration testing
• Performance optimization
• SoC memory driven scenario creation
• Efficient debugging of very long tests
• SW/HW tests

Verification Solutions

Cadence offers a wide range of tools that will help you to speed up the verification project while relying on the highest quality and maturity verification tools in the market.

PHY Level

During PHY level verification, DFI is the device under test and a simulation environment is created around this based on

• LPDDR5 Memory Model to simulate the memory device, it should check that your DUT is compliant with JEDEC LPDDR5 and all vendors
• DFI VIP to simulate the DFI PHY or MC components, it needs to check that your DUT is compliant with the DFI 5.0 spec for LPDDR based on your timing requirements
• LPDDR5 DFI test suite to generate all the scenarios needed to ensure that you are covering all the corner cases defined in the specifications
• Cadence Score boarding makes data integrity and cache coherency checks

Cadence LPDDR5 Memory Model (MM)

Cadence Memory Models are the gold standard for memory interface verification. Used by more than 500 customers for functional signoff, Cadence Memory Models provide support for 10,000 memories spanning 100 memory interface types and 85 memory manufacturers available in Cadence.

Features and Key Capabilities

• Easy integration to PHY/IP level verification solution
• Plug-and-play to System-level verification solution
• 100% LPDDR5/LPDDR5X JEDEC support
• Full feature Verification plan and Coverage Model

DFI MC VIP (DDR PHY Interface)

The DFI specification defines an interface protocol between memory controller logic and PHY interfaces, with the goal of reducing integration costs while enabling performance and data throughput efficiency. The Cadence Verification IP (VIP) for DFI provides a mature, highly capable compliance verification solution for the DFI protocol. The VIP supports the simulation platform and enables metric-driven verification of IP. DFI VIP supports both the memory controller (MC) traffic generation and the PHY component, which samples from the DFI interface and drives to the memory interface for different memory variants. The VIP for DFI is compatible with the industry-standard Universal Verification Methodology (UVM) and supports all leading simulators.

Features and Key Capabilities

• 100% support for DFI specification 5.0/5.1/4.0 and LPDDR5/5X specifications
• Generates constrained-random bus traffic with predefined error injection 
• Hundreds of protocol and timing checkers to easily catch design bugs
• On–the–fly controllability by callbacks
• Easy/Automatic configurability
• Error Injection support
• Easy debuggability

Triple Check – Cadence Protocol Compliance Suit

The Cadence TripleCheck IP Validator for DFIMC adds another layer of verification capability and provides an easier way to ramp up quickly on your verification tasks. In addition. It also helps the team to assess the project's progress by tracking the overall coverage grade week by week. LPDDR5 DFI test suite generates all the scenarios needed to ensure that you are covering all the corner cases defined in the specifications. The coverage model is not connected in any way to the test suite, which means you can always run the legacy tests and collect coverage from those runs. The TripleCheck for DFIMC covers the Memory Models DDR4, DDR5, LPDDR4, LPDDR5, HBM2E, and HBM3.

IP level

Depending on the IP component that you are developing, whether your DUT is a PHY, MC or memory device, an appropriate verification environment will be required.

In this environment, you will be able to reuse the same memory model from your IP level environment while using the LPDDR5 DFI VIP in monitor mode to verify that all training and transactions passing on the DFI interface are compliant with the DFI 5.0 specification and to your specific timing requirements. During the LPDDR5 IP level development, your verification scope will need to ensure that your IP is spec-compliant to DFI 5.0 for the interface between the MC and PHY, and  LPDDR5 spec-compliant depending on the specific vendor datasheet of the Memory vendor. 

SoC Level

This level offers different types of challenges, here we have complete system as a memory sub-system part of it. Regardless if you want to verify your SoC over simulation or emulation, three major tools will be needed:

• A set of system traffic libraries to generate all the system scenarios to verify
• A system verification scoreboard to verify the correctness of the data traffic and cache coherency of your system
• System Performance Analyzer: Tool to identify design’s bottleneck, it enables the discovery of performance degradation with in-memory sub-systems, interconnects, and peripherals.

Summary

This Cadence Verification IP (VIP) supports the JEDEC^® Low-Power Memory Device, LPDDR5 standard. It provides a mature, highly capable compliance verification solution that supports simulation, formal analysis, and hardware acceleration platforms, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. The VIP for LPDDR5 is compatible with the industry-standard Universal Verification Methodology (UVM), runs on all leading simulators, and leverages the industry-standard Cadence Memory Model core architecture, interface, and use model.

Learn more

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https://ip.cadence.com/ipportfolio/verification-ip/memory-models

https://www.cadence.com/en_US/home/tools/system-design-and-verification/verification-ip/verification-ip-catalog.html

https://www.cadence.com/en_US/home/tools/system-design-and-verification/system-vip.html