Maximise Verification Reuse with Cadence Perspec System Verifier

Are You Tired of Countless Hours Manually Creating Complex System-Level Coverage-Driven Tests to Verify Your SoC?

During the verification process, teams often work independently, creating test suits from block level to subsystems and SoC. This results in many duplicated efforts across projects, with each platform having its language and format for specifying tests created by different teams. The primary concern in the design verification is achieving the desired coverage in less time. To improve efficiency, abstraction, and reuse are critical ingredients.  Recently, Tessolve, a leading global engineering service and solution provider, showcased their practical experience in verification reuse from IP to subsystem, SoC, and silicon at CadenceLive India, using the Perspec system verifier. Emulation and FPGA prototyping are also essential tools in the verification process. Trusting in these methods can bring your designs to fruition quickly and confidently. To ensure the success of complex designs, it takes more than just simulation. Verification engineers at Tessolve leveraged the scenario-solving and full automation capabilities of the Perspec system verifier, and they were able to generate scenarios and manage the full scope of the tests required.

How to Improve Verification Reuse

PSS aims to enhance productivity by providing a unified test generation framework that enables collaboration and test intent reuse at every level. Leveraging PSS, we can reuse the model across hierarchy, platform, and project levels.

• Hierarchy (Block, Subsystem, SoC, system)
• Platform (simulation, emulation, FPGA, Silicon)
• Project (reuse from the same model from one project to the next)

It can generate various tests, from graph-based to constrained random tests. With minimal changes, it enables one-time model development and test case generation and reusability across different teams and platforms such as level, sub-system, and system level.

Why Tessolve Adopted the Cadence Perspec System Verifier

The sheer complexity of multicore, cache-coherent, low-power SoCs at Tessolve presents many permutations that require testing of complex interaction between processing cores, caches, and SoC IP components. The design verification team at Tessolve noticed it is tough to generate scenarios and achieve the desired coverage with manual techniques. They wanted to improve test case throughput, productivity, scenario coverage, test case quality, and ease of debugging. They needed to create reusable tests from IP to sub-system to SoC, including software layers and portability across verification platforms and projects.

The Perspec System Verifier can effectively validate SoC's performance, function, and power by using an appropriate level of abstraction. It is a portable platform that can be reused across different scopes, including hardware-aware software, from IP to the system level. This approach focuses on both vertical and horizontal reuse - vertical reuse covers IP level verification to subsystem to SOC level verification. In contrast, horizontal reuse involves using the test intent across virtual prototype platforms, simulation, emulation, and FPGA. Ultimately, this approach helps to reduce the time and effort spent on creating tests. PSS provides a single abstract specification of verification intent, which allows tools to generate target-specific implementations of the test for the various platforms involved in verification. This frees teams to focus on what should be tested instead of implementing the same test multiple times. PSS can also automate the process by randomly generating scenarios subject to the rules and constraints defined in the abstract specification, maximizing coverage, and ensuring efficient execution of a wide range of tests on multiple platforms. The key benefits that led to the adoption of Perspec system verification by Tessolve include:

• Ease of modeling
• Ease of describing and visualizing complex high-level test intent
• Tests are less prone to coding errors, typos, etc. And are more readable
• Fast constraint solvers enable more flexible modeling and reusability
• Reuse from IP to SoC and software level
• GUI (UML diagram) for test case creation and analysis
• Easy to use drag/drop option for solution creation
• Provides the coverage details even before the simulation
• Keeps user informed about the coverage of test cases
• Complete/ partial scenario creation.
• Automatic creation of various solutions

Use Case

Tessolve considered the development of models using the Perspec system verifier of different IP blocks, which can be reused across IP, subsystem, and SoC levels as per the block diagram below.

These models are developed using Perspec tools and can be written in PSS/SLN (system-level notation) language. The developed models are executed during simulation with Specman e’ testbench verification and Linux execution at the SoC level. Component, action, and dataflow are the main building blocks for model development.

The model developed is used for scenario creation. Perspec can automatically create different valid scenarios.

Once the individual PSS model is developed, it can create subsystem scenarios. Here, the scenarios from different IPs can be combined to create a subsystem scenario, thus enabling system reusability, as shown below.

Domain experts create the model and scenario descriptions, which enable verification and validation engineers to create system-wide tests.

Conclusion

Cadence Perspec System Verifier is a robust tool that automates the generation of test cases. It creates test cases in the C language, which can be used with various testbench environments. Tessolve has extensive expertise in developing reusable models across various platforms, including simulation, emulation, FPGA prototyping, and post-silicon. According to Tessolve, Perspec System Verifier has saved them a significant amount of time in test case development and is free from errors compared to manual test case development. Cadence Perspec System Verifier can be leveraged at various verification levels, such as IP, subsystem, and SoC.

The experience with Perspec and the PSS methodology resulted from a joint project between Infineon, Tessolve, and Cadence. Infineon was responsible for the project, device under test (DUT), and verification environment ownership. Tessolve managed the project, developed models, and executed the project. Meanwhile, Cadence's SDE team (System Design Enablement) provided PSS modeling, methodology, and tool support. It was presented during the CadenceLIVE India’23, If you missed the chance to catch them live, register at the CadenceLIVE website to watch it and all other presentations.