Metric-Driven Verification in a Box...

In my last few posts, I was explaining our focus here in Cadence Verification on creating the OVM to enable an industry wide VIP eco-system, and trying to make verification more of a closed-loop process with our metric-driven verification methodology.  In case you missed the announcement about expanding our VIP portfolio back on October 15th, we just made it a lot easier for you to experience the benefits of the combination of the OVM and metric-driven verification, (not to mention the fact that we have significantly grown the OVM VIP eco-system).  The announcement is about how we have significantly expanded our VIP portfolio to offer support for over 30 standard protocols.  Each "Universal Verification Components" (UVC) within the portfolio is built according to OVM with support for both e and SystemVerilog interfaces, and most of the UVCs have built-in metric-driven verification capability.  If you are building a SystemVerilog or e OVM (or eRM) testbench, since our UVCs follow the same methodology, you can easily plug one into your environment and save yourself the time and effort of coding up that part of your testbench.  Since most of our UVCs are also pre-built for metric-driven verification, this helps you to quickly experience the full power of using constrained-random, coverage-driven verification.  Each of these UVCs includes an "executable" verification plan which captures all of the features of the specific protocol that need to be verified, and then each feature in the plan is mapped to a coverage or check metric that executes within the UVC code.  There is also a library of constrained-random sequences which can be run to fill much of the functional coverage metrics.  As our VIP Marketing Person likes to say, this is "metric-driven verification in a box."  If you want to find out more about our expanded VIP portfolio, you should check out the product web page.

 Mike Stellfox