User Views -- Migrating From FPGA-Based Prototyping to Palladium

In recent posting published by John Cooley on Deepchip.com, users compared FPGA-based prototyping systems to Palladium systems. I always like to read responses that reflect user views -- as we all know these are always more credible.

I would like to summarize the inputs to this posting here:

Key Palladium benefits mentioned:

1. Fast Tunaround/Build time (after you find a bug) takes minutes in Palladium vs. hours/days for FPGA-based prototyping. The faster times increase productivity. No dedicated engineer needed for Palladium compilation - "everybody can do it."

2. Visibility into all registers, nets and memories with large trace depths saves debug and emulation time. Finding more bugs (3-4X) with fewer people (1/2).

3. Configurable -- can maintain multiple versions of the design in a simple way in Palladium

4. Multi-user capability helps testing in parallel multiple sub-systems

5. TCL scripting automates compilation process

6. SpeedBridge adapters automatically adjust the external live interfaces for emulation speed

7. Can be used for SW development and boot-up OS earlier (when RTL is generated, even is it is unstable)

8. Scalable capacity

9. Predictable performance

10 . Lower cost of ownership (resources for support) and higher reliability

Key FPGA-Based prototyping benefits:

1. Higher performance/speed reduces run-time, especially when the design is more stable and SW development is the primary use model.

2. Cost of materials - if you need multiple platforms as replicants

3. Can run at real-time in some situations

In general, the conclusion of most of the users is that these two solutions are complimentary to each other and being used in different phases of the design development process. It would be nice if there was more automation from one system to another.  

If you have more comments and did not provide a submission to John, I will be interested to hear from you here.

Ran Avinun