Moving Low Power Chip Design up to the System Level

Anybody watching Cadence these past couple years has probably noticed how we're pretty serious about investing in making tools for low-power design.  While most of the attention in the EDA industry up to now has been on how to optimize chip power consumption while working at the RTL/gate level, that is going to change drastically this year, where Cadence's focus will extend to optimizing chip power consumption while working at the ESL/System/Chip Architecture level. 

Optimizing for power at this higher level is obviously where designers can make the biggest impact, and this year we'll be rolling out a bunch of new capabilities in this area.

For anyone interested in where Cadence is going with System Level low power SoC design, I should let you know Cadence is running a System Level techtorial-workshop series across North America starting in a couple weeks.  Click here for more information and to register.

Here is a short preview of what you can expect to hear at this event.

 If the video does not load click here.

What's different about this event-series?  First, they cover three tools that are fairly unique in the industry:  InCyte (chip estimation), C-to-Silicon Compiler (high-level synthesis) and Palladium Dynamic Power Analysis.  Second, the key focus however will be on teaching (rather than selling!) designers how they can be used together.  More than half of the day is dedicated to "hands-on" workshops where people get to test-drive the tools on real designs (under the competent supervision of an expert AE).

So while some seminar attendees in the past have asked for more technical depth/details, this time there's a likelihood that people will ask for less!  (In any case, the free food as always, will be pretty good!)