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If you’re leaving 2018 with the feeling that your SystemVerilog skills are lacking, don’t worry—there’s a new series of Cadence Training Bytes to help you hit the ground running in 2019. Here you’ll find eight new YouTube videos all about SystemVerilog classes.
You can find the first video here.
Here’s a quick table of contents:
SystemVerilog Classes 1: Basics
This video goes over the basics of what a SystemVerilog class is—how to create an instance of a class, what a class can and can’t contain, and what they can be used for. It also goes over how SystemVerilog classes compare to the C++ or Java classes you may be familiar with.
SystemVerilog Classes 2: Static Members
Here, you can learn about the static properties and methods of a class—a property or method shared by all class instances. If you’ve ever wanted to access a member function of a class you haven’t created an object for yet, the Static keyword is here for you.
SystemVerilog Classes 3: Aggregate Classes
An Aggregate Class is a class that has properties that are also classes. It’s similar to module instantiation. Having an aggregate class can help you define a slightly different relationship that that of a parent and child class; since the member classes of an aggregate class don’t necessarily have to derive information from the aggregate.
SystemVerilog Classes 4: Inheritance
Inheritance in SystemVerilog is similar to what you may already know from other object-oriented programming languages. To inherit a parent’s properties into a child class, use the “extends” keyword in the class declaration. A child class can add more members to a parent’s class or override existing members in a parent class.
SystemVerilog Classes 5: Polymorphism
You can only extend from one parent in SystemVerilog—how do you get around this? Polymorphism comes to the rescue! Using an array of handles, one can dynamically select which subclass you want to use easily, without having to make so many tedious declarations.
SystemVerilog Classes 6: Virtual Classes and Methods
If you’re using polymorphism, you might be running into issues where a method called through a handle isn’t calling the right function along the inheritance line. Virtual classes and methods can help out with that—a virtual method is resolved according to the contents of the handle. For more information on that, check out this video.
SystemVerilog Classes 7: Class Randomization
If you want to randomize a class property, you can use rand or randc. Rand creates random content with uniform distribution, while randc is random cyclic—it iterates through all values without repetition at least once. Once you’ve declared a variable as rand or randc, you can call the randomize function, which is an un-redefinable function native to all classes that will randomize the data held by variables marked as rand or randc.
SystemVerilog Classes 8: Class Constraints
If you don’t want a random value to be any value, you can use a constraint—this allows you to create a range in which random values can be generated. Constraint members are normal class members and can be inherited just like any other. Check out the video for more information on what constraints can and can’t do.
There you have it—a selection of eight Training Bytes to get you started learning about SystemVerilog classes. To view other Training Bytes you might be interested in, check here.