New VIP for ARM AMBA 5 CHI Issue B

In coordination with the announcement of the new ARM® AMBA® 5 Coherent Hub Interface Issue B, Cadence is announcing the availability of its AMBA 5 CHI Issue B Verification IP (VIP) to address the complexity challenges of enterprise SoC development for server and networking applications. The VIP provides support for the AMBA 5 CHI Enhancement Specification, which is part of the ARM AMBA 5 family of protocols, the next generation of the ARM interface standard.

ARM AMBA CHI

ARM AMBA open standards for on-chip communication have been widely adopted throughout the industry, providing a rich ecosystem for re-usable intellectual property (IP) products and tools to build systems-on-chip (SoCs) across a wide range of applications including mobile, networking, server, automotive, and internet of things (IoT). The AMBA enhancements provide new capabilities for additional performance, improved efficiency, and data protection within a system.

So, what is AMBA CHI, and why do we need an updated specification?

SoCs today are complex systems that have what is called a hub—a high-performance interconnect central to the SoC, responsible for connecting the high-performance processors and memory controllers. To meet the increasing performance requirements of these SoCs, it is imperative that this interconnect never become the bottleneck in the system. There should never be a time when critical system resources, which are invariably the memory controllers, are inefficient because of the interface and interconnect being used. AMBA 5 CHI targets the interface to the coherent hub, hence the name "Coherent Hub Interface."

AMBA CHI was first introduced in 2013, to support the ARM architectures of the day. But since then there have been several enhancements made to the ARM cores for performance, latency, and security, which now require an update to the interconnect specification.

These enhancements in AMBA 5 CHI Issue B include:

• ARMv8.1-A large system extensions for more memory, extended virtual machine IDs, and far atomic operations for high-frequency updates to shared data
• Performance extensions and latency reductions like cache stashing and direct data return
• Enhanced RAS aligning with ARMv8.2-A architecture for end-to-end data protection and poison signaling

Cadence VIP for AMBA 5 CHI Issue B

Why is a commercial VIP essential to the design process? After all, companies have been designing their own VIP for several years.

To a certain extent, all VIP offer the same value proposition to designers: rapid development time. The VIP allows customers to focus on their key areas of expertise rather than develop an in-house verification IP solution, speeding SoC development. But by far the main reason commercial VIP are a necessity is that they are independent from the designers who develop these interconnect interfaces. If the designers who developed these interfaces also designed the VIP, then it’s fair to guess that any assumptions they made about the interface specification in the design, they would also make in the VIP.

Cadence VIP go far above and beyond this basic requirement, offering a slew of added benefits.

The availability of the new Cadence VIP for ARM AMBA 5 CHI Issue B will aid in the rapid adoption of the new AMBA 5 CHI Issue B standard. Developed through close coordination with ARM, the VIP offers the following benefits to customers:

• Product maturity: The AMBA 5 CHI Issue B VIP is already being used by early adopters in the field on several different designs
• Complete and comprehensive solution: It includes all forms of CHI transactions, comprehensive checking, coverage models, and advance debug capabilities
• Reduces time to market with ARM CoreLink^™ CMN-600 designs: The VIP was developed with an in-house CoreLink CMN-600 design to speed-up time to market
• Enables SoC data integrity and coherency behavior: The VIP is complimented by the Cadence Interconnect Validator (IVD), which enables system-level data integrity for coherent and non-coherent interconnects
• Offers performance analysis capability: It is complimented by the Cadence Interconnect Workbench (IWB), which provides performance analysis capabilities to help customers optimize system performance

In addition to the benefits listed above, the new AMBA 5 CHI Issue B VIP provides a highly capable verification solution that supports simulation, formal analysis, and hardware acceleration platforms, making it applicable to IP, SoC, and system-level verification. This ensures that all the stages of verification—through the entire design cycle—use the same VIP and offer consistent results. The AMBA 5 CHI Issue B VIP is compatible with the industry-standard Universal Verification Methodology (UVM) and runs on all leading simulators, enabling verification engineers to efficiently perform in-depth verification tasks. 

The AMBA 5 CHI Issue B VIP is available in three versions:

• AMBA 5 CHI Issue B VIP, which is primarily intended for simulation
• AMBA 5 CHI Issue B AVIP (accelerated VIP), which is intended for use with Cadence’s Palladium platform
• AMBA 5 CHI Issue B ABVIP (assertion-based) VIP, which is intended for use with Cadence’s JasperGold formal platform

For more information, take a look at the Cadence VIP for AMBA 5 CHI Issue B webpage.