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With new PCIe 6.0 Base specifications rolled out, the move from NRZ (non-return-to-zero) to PAM4 (4-Level Pulse Amplitude Modulation) is no surprise. To address the Nyquist frequency issues at 64GT/s, which doubles to 32GHz which further causes frequency dependent loss increased to 70dB, PAM4 was introduced.
Use of PAM4 signaling address the issues related to integrity, channel loss and backward compatibility but increased the complexity to verify designs.
Now till PCIe 5.0 for Lane margining at receiver, NRZ (non-return-to-zero) was used. With PCIe 6.0, PAM4 was used instead.
PAM4 is a multi-level signaling technology that transmits two bits per unit interval (UI) as opposed to the conventional NRZ (non-return-to-zero), which transmits only one bit per UI.
PAM4, since two bits are encoded using four voltage levels in the same UI leads to a change in eye diagram from PCIe 4.0 to PCIe 6.0.
For more information on PCIe 4.0 Lane Margin at receiver follow Demystifying PCIe Lane Margining Technology
With PAM4 signaling additional voltage levels reduce the eye height by a factor of 3 in PAM-4 which further caused the Eye width to move from 1/2 to 2/3 of NRZ. Now we have three eyes instead of one. The eye is not only smaller in the Voltage domain but in the Time domain as well.
Since no two voltages are the same, due to the voltage differences these three eyes are never the same width/height.
The middle eye is the most symmetrical among all three and the Top and bottom eyes rarely match the middle eye.
Talking about commands, the Step Margin commands apply to all eyes simultaneously, so there is no difference in executing Margin Commands. The Software/Margin Command flow remains the same.
To achieve Lane Margining at the receiver, as defined by PCIe 4.0 specifications Control SKP Ordered Sets are used to send commands.
The format of PCIe 6.0 Control SKP changed as used 1b/1b encoding, and hence the bit field positions in Control SKPs. Below is the comparison of the PCIe 6.0 Vs PCIe 4.0 Control SKP Ordered Set.
Control SKP Ordered Set 1b/1b (PCIe 6.0)
Control SKP Ordered set 128b/130b (PCIe 4.0)
Apart from above, since the eye height/width is changed, PCIe 6.0 introduced four new parameters: MNumTimingStepsPAM4 , MNumVoltageStepsPAM4 , MMaxTimingOffsetPAM4 and MMaxVoltageOffsetPAM4
Now, the most important question is- How to verify your design?
Cadence PCIe VIP package offers intensive verification for PCIe based Designs with VIP configurations and parameters to ensure quality, maintaining backward compatibility and capturing ‘hard to find” corner case scenarios.
In addition, Cadence VIP’s Triple Check which is an inbuilt ready-to-integrate suite, enables a hassle free and exhaustive verification of your design.