Functional Verification Blogs

PCIe (Peripheral Component Interconnect Express) has long been the backbone of complex systems, and provides a high-bandwidth, high-performance link for interconnecting devices imposed by cloud-based computing power, storage capacity network bandwidth, artificial intelligence automotive platforms. PCIe 6.0, in turn, is the most important and most disruptive update to the PCIe standard since PCIe 3.0 almost a decade ago. 

The PCIe 6.0 introduces a new physical layer change, with PAM4 (Pulse Amplitude Modulation with 4 levels) signaling to replace NRZ (Non-Return to Zero), a key ingredient in the generational bandwidth doubling effort. Rather than traditional 0/1 high/low signaling, PAM4 uses 4 signal levels so that a signal can encode for four possible two-bit patterns: 00, 01, 10 and 11 per Unit Interval (UI) without increasing the transmission frequency. It doubles the data rate to 64 GT/s, adequate bandwidth over PCIe 5.0 to 256 GB/s of throughput and retains the same maximum x16 lanes. 

The additional signal states of PAM4 results more fragile signal than an NRZ. The PCIe 6.0 counters this by incorporate a combination of light-weight correction through FEC (Forward Error Correction) and strong detection and retry through CRC (Cyclic Redundancy Check) scheme to maintain the data integrity and low latency being a load-store protocol. Through these two methods, the result is a correlation between errors on a Lane and across Lanes: FEC operates on the principle of sending redundant data that can be deployed to correct some errors at the Receiver. CRC is an error detection code used to authenticate packet transmission between the sender and the receiving end, resulting in the eventual correction through Link Layer Retry.

The error correction needs to operate on fixed-sized packets, hence the adoption of  FLIT (Flow Control Unit) for PCIe 6.0. The TLP header changes TLP Header Base followed by 0 to 7 additional DW of OHC (Orthogonal Header Content), end-to-end TLP prefixes integrated into the header, along with other changes to improve the robustness and extensibility for TLP content and structure. DLLPs are fixed based upon FLIT mode. Since error correction happens on FLIT, we have the CRC check as well as Retry at the FLIT level. Once the Link operates in FLIT mode, any speed change to lower data rates will also have to use the same FLIT mode. Thus, once enabled, FLIT mode is followed in the Link, irrespective of the speed or 8b/10b and 128/130 block encoding.

Beyond PAM4, FEC, and FLIT, PCIe 6.0 improved various improved power consumption with L0p (L0 Partial) that replaces L0s for FLIT Mode. The new state L0p is symmetric and maintains at least one active Lane that supports scalable power consumption and ensures uninterrupted traffic flow, even during width transitions. The Link always trains in the highest possible width and subsequently can modulate its width depending on the bandwidth need in FLIT mode. The Shared Credit Pooling allows multiple VCs to share the pool and reduce the cost. It is optional for a receiver to implement but mandatory for a PCIe 6.0 device to support as a transmitter.

One important that has not change is that , PCIe 6.0 retains backward compatibility with all five older generations of PCIe, which could mean the PCIe slot on motherboards do not look any different. The PCIe protocol's intricate nature requires verifying interoperability and backward compatibility in multi-layer functionalities, previous spec generations, diverse topologies, and configurations. On top of that, the new PCIe 6.0 introduces disruptive changes at all layers, which requires require a comprehensive functional verification and testing approach.

Furthermore, in the last few years, their efforts have taken on an increased level of importance, as other major interconnect standards are building off PCIe. CCIX (Cache Coherent Interconnect for Accelerators), Intel's CXL (Compute Express Link), and other interfaces have all extended PCIe and benefit from PCIe improvements. So PCIe speed boosts serve as the core of building ever-faster and more interconnected systems, which requires require advanced system-level verification.

To be sure, taking advantage of all these new features and enhancements with the latest generation of PCIe while maintaining backward compatibility requires advanced system-level verification to ensure at a first order that things did not break and then to verify the intricate new changes. 

More Information:

• For more info on how Cadence PCIe Verification IP and TripleCheck enables users to confidently verify these new disruptive changes, see our VIP for PCI Express page and TripleCheck for PCI Express 
• For more information on PCIe in general, and on the various PCI standards, see the PCI-SIG website.