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Handheld devices have evolved immensely over the past decade. Today's smartphones, with their intricate arrays of sensors and computational power, far surpass their predecessors in complexity. These modern devices rival the capabilities of past supercomputers. When you factor in the intricate power management demanded by battery constraints, verifying these devices becomes a uniquely challenging task.
Figure 1: The complexity of low-power verification
Many of the strategies used to make these complex devices run with strict power requirements pose challenges for traditional verification. Frequently, low-power devices will reduce the voltage/frequency or shut off low-activity or inactive areas of the device to save power—and if these areas are not active, how does one ensure that they work correctly in the context of the rest of the system? Furthermore, in these power shutoff domains, often one must retain the chip state in order to make sure that everything works correctly when the domain becomes active again. This sort of state retention is not something most constantly powered devices need to worry about.
This diversity of mobile equipment demands advanced low-power verification techniques to address their specific needs, and these must be considered at the start of the development cycle. How will designs and verification account for varying power requirements? How does one handle RTL that contains constructs that don’t operate correctly in low-power environments? Simply using traditional power-reduction techniques during synthesis and physical design is not enough. Specific power-aware design and verification must be applied.
Low-power design follows the methodology in IEEE 1801 UPF and is rooted in the use of a power control module (PCM). The PCM is custom-crafted for the design to address the power intent of the various domains of an SoC. It is responsible for the management of power control signals, clocks, and resets. This controls the power supply network (PSN), which is the system of supply ports, nets, power switches, and the various interconnections between these. The PCM is what adds verifying low-power behavior to traditional functional verification—but it is still not that simple.
Xcelium, coupled with its Low-Power App, implicitly models power shutoff (PSO) behavior, but a strong awareness of the PSN is required to understand how PSO will affect logic flow through a chip, specifically the propagation of unknown, “X,” values.
X-propagation is one of the key challenges with low-power simulation, and debugging it is a hot topic in the industry. How does one plot the movement of unknown values through a design? State retention through PSO can help reduce the number of X values uncovered through verification, but these values can still exist, and understanding how they can be resolved so that they do not affect the powered-up areas of a design is critical to reaching one’s goal of a bug-free design.
Don’t worry, though: Cadence has you covered. Between Xcelium Logic Simulator’s low-power verification features and Verisium Debug’s powerful debug capabilities, one can verify their low-power designs more efficiently than ever before. We will explore these features and debug capabilities in a further installment, as well as a discussion on how adding in mixed-signal design adds a whole new complexity to verification.