Pre-Silicon Edge AI Verification: Skymizer and Palladium Z3 System Studio

As large language model (LLM) inference expands beyond hyperscale data centers into power-, memory-, and thermally constrained edge devices and enterprise-controlled on-premises systems, silicon complexity and verification workloads are increasing rapidly. Designing a complex architecture is only part of the challenge; validating the tightly coupled software stack—including compilers, runtime kernels, device drivers, high-speed interfaces, and memory subsystems—well before first silicon returns from the foundry is equally important.

Waiting for physical chips to begin system-software bring-up introduces significant program risk and can delay time to market.

Skymizer addressed this challenge by using Cadence Palladium Z3 System Studio to accelerate verification of its Language Processing Unit (LPU) and begin software bring-up months earlier.

Breaking Through the Simulation Wall

Skymizer develops LPU IP and silicon for on-device, edge, and on-premises LLM inference, supported by advanced compiler toolchains. Its architecture targets predictable latency and energy-efficient inference across constrained devices and enterprise systems.

Validating this next-generation architecture introduced three critical engineering hurdles:

• Workload scale: Representative LLM verification workloads can require billions of clock cycles across transformer layers, memory traffic, and host-device interactions.
• Hardware-software integration: Validating pure RTL in isolation is no longer sufficient. AI compilers, kernel runtimes, operating system drivers, PCIe Gen5 interfaces, and high-bandwidth LPDDR subsystems all must be validated together.
• Simulation performance: Traditional RTL simulators take too long, often requiring days or even months to fully execute comprehensive AI workloads.

FPGA prototyping is valuable for high-speed software validation once a design is sufficiently stable. During earlier, iterative RTL bring-up, hardware emulation provides faster compile-debug turnaround, cycle-accurate execution, and deeper hardware-software visibility.

Shifting Software Validation Left

Skymizer deployed its pre-silicon LPU RTL model on the Palladium Z3 platform and connected it to an Ubuntu host through a PCIe Gen5 SpeedBridge and Emulation Development Kit (EDK).

This environment allowed real workloads, compilers, and drivers to interact with a cycle-accurate representation of the LPU before physical silicon was available.

For this design, the Palladium platform reduced compilation turnaround to approximately 10 minutes, enabling hardware and software teams to modify, compile, debug, and test multiple iterations within a working day.

Demonstrating Significant Acceleration

Skymizer recorded substantial performance gains when running AI workloads on Palladium Z3:

Workload	RTL simulation	Palladium Z3	Acceleration
TinyStories 260K	13.5 minutes	3 minutes	4.5X
Llama 3.2, 1B parameters	5.2 days	20 minutes	374.4X
Llama 3.1, 8B parameters	77 days, projected	36 minutes	3,080X

 

In these tests, acceleration increased with workload scale. For Llama 3.1 8B, the equivalent RTL-simulation runtime was projected at 77 days, while Palladium Z3 System Studio completed the same verification workload in 36 minutes—a 3,080X wall-clock acceleration. Acceleration figures compare the wall-clock execution time for equivalent pre-silicon verification workloads; they do not represent production inference throughput.

This acceleration allowed Skymizer to execute realistic workloads earlier, validate interfaces sooner, and complete more hardware-software iterations during development.

Accelerating Debug and Root-Cause Analysis

Speed alone is not enough. Engineers also need visibility into hardware behavior when software encounters an unexpected condition.

Using Palladium FullVision and the Software Debug Link, Skymizer could correlate software execution with cycle-by-cycle RTL activity at emulation speed. Engineers could investigate issues without recompiling the design solely to add debug instrumentation.

This brought hardware and software teams into a common verification environment, enabling integration issues to be identified and resolved earlier.

Reducing Verification Time by More than 90%

By adopting hardware-assisted verification, Skymizer:

• Reduced end-to-end verification time by more than 90%
• Shortened LPU and PCIe verification cycles from weeks to days
• Started software bring-up months earlier
• Improved software readiness before first silicon

Skymizer’s results demonstrate that market velocity increasingly depends on pre-silicon hardware-software validation.

In the fast-moving advanced AI SoC landscape, hardware design and software enablement cannot be sequential. Skymizer's experience shows how validating the complete system stack before first silicon helps engineering teams reduce program risk, protect schedules, and improve software readiness for edge and on-premises deployment.

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