• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Blogs
  2. Verification
  3. "Day 0" of CDNLive San Jose 2008
jvh3
jvh3

Community Member

Blog Activity
Options
  • Subscribe by email
  • More
  • Cancel
CDNLive San Jose 2008
MDV techtorial
System Verification

"Day 0" of CDNLive San Jose 2008

9 Sep 2008 • 1 minute read

Quick report from CDNLive Day 0 (I've labeled it that since this initial day was devoted to techtorials, ahead of the main events and papers tomorrow) First, the promised photos from the day's events are posted here.

* MDV techtorial snapshot: from the segment I saw, there was a lot of Q&A.  This came as no surprise to me since I've seen the presenter, Solution Architect Paul Carzola, teach this material before.  The "secret" to his success is that he is an expert at drawing people out by engaging them with examples from real life anecdotes from his extensive work with customers.

* Stopping in on the System Level Verification techtorial rewarded me with of hearing a segment presented by a Palladium customer (a stealth mode startup called Novafora) on their usage and success with the Palladium for emulation.  This engineer was clearly making an impact on the crowd, because people were ignoring the buzz of their Blackberries and instead scribbling down notes on the conference stationary.

* Curse you demo gods!  The demo gods were terribly cruel to my colleague on "Team ISX" Leonard Drucker, when they foiled his efforts to illustrate some HW/SW co-verification issues live with a quick 5 minute demo from his Linux laptop. Argh!

* With the System Verification Team on a roll, I was compelled to stay for the "Ask The Experts" panel, comprised of the Novafora engineer, Jai Kumar of Sun, and Cadence Architects from different sub-specialties.  One of the discussion points that stuck in my mind (given my interest in metric driven HW/SW co-verification) is the struggle the customers can have trading off putting in functional coverage monitoring vs. capacity in the box (i.e. the accelerator or emulator's gate capacity).  i.e. the coverage monitors have some overhead associated with them, which can come into play when you are filling up the box to the brim with gates.  Given how important coverage is to finding bugs, I don't envy having to make such a tradeoff.

That's it for "Day 0".  Tomorrow is the [Ed Sullivan voice] "the really big show" with the key note speakers, roadmaps, first of customer papers, and (I think) the arrival of the poker champion!

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information