Get email delivery of the Cadence blog featured here
The wait is finally over—the Rapid Adoption Kit (RAK) for verifying the power intent of low-power mixed signal SoCs is here! The RAK is a tutorial designed to clearly show, through example, how to verify one of the most critical technology convergences in IoT devices. It’ll talk about the differences in verification of a processor-based design whether it’s powered internally or externally, how to verify SPICE, SystemVerilog Real Number Models, AMS, and Verilog models in the same environment, the new features in UPF 2.0 regarding power intent specification, and highlight issues you might face while verifying low-power SoCs.
Of course, all of this IP was developed by Cadence, and the testbench was created using UVM. The source code is Apache-licensed to make it easier for you to use.
In the example provided by the RAK, the top level of the SoC is a processor-based design where an off-chip voltage regulator drives the power supplies on the chip. This design is referred to as the CORE.
Figure 1: Block Diagram and Low Power Architecture
Off-chip, the voltage regulator provides 5V power to CORE. Inside CORE are two blocks—ANALOG_TOP and DIGITAL_TOP. ANALOG_TOP has the on-chip power supplies, while DIGITAL_TOP contains the processor (PROC) and its subsystem.
Figure 2: Block Diagram of ANALOG_TOP
How is the power reduced? There are two main ways: through Power Shutoff (PSO), where the parts of a design that aren’t in use are shut down to conserve power, and through Multi-Supply Voltage (MSO), which lowers the supply voltage when the timing constraints allow that to be done without sacrificing performance.
The different power needs for different parts of the chip are called the “power intent”, which is specified using the Unified Power Format (UPF) 2.0.
Usually, in mixed-signal SoCs, the performance of on-chip power supplies isn’t all that important to the digital IP. In low-power simulations, however, those on-chip power supplies become a lot more relevant, as they’re being toggled on and off to save power regularly. This means that low-power mixed signal simulations can take advantage of the variable power intent modeled by UPF.
So—how does UPF model power intent? UPF does so through supply nets, which are modeled as SystemVerilog structs containing a state (of which there are four different ones) and an integer “voltage”, that holds the value of the voltage in microvolts.
There are four different states that can be mapped to the “state” field of the supply net: OFF, UNDETERMINED, PARTIAL_ON, and FULL_ON. In this screenshot of the RAK, you can see the state of the VDD_5V net transition from OFF to PARTIAL_ON, among other state transitions described in the “Power Up” power state.
Figure 3: The “Power Up” power state
This RAK’s example SoC passes through six power states—Power Up, Load SRAM, Power Up PROC, Low Power Mode—Power Down, Low Power Mode—Power Up, and LDO Shutdown. Check out the RAK manual for pictures and additional information regarding each power state.
If you have questions about verifying power intent for low-power mixed-signal SoCs, this RAK is exactly what you’re looking for. Check it out here.