Get email delivery of the Cadence blog featured here
If you’re looking for an example of how well the Cadence flow fits together, look no further than Renesas and their experience using the Cadence System Testbench Generator and System Performance Analyzer alongside Perspec and Palladium. With development time requirements shrinking while designs grow, verification engineers and chip designers need access to every advantage they can get, and there’s few ways you can improve your development cycle more than with Cadence System Testbench Generator, System Performance Analyzer, Perspec, and Palladium.
Renesas was looking to verify bus performance in their chips by analyzing bandwidth and latency over time. This is tricky because bus verification takes a long time and the testbenches are challenging to develop thanks to the specific allocations required for both active and passive VIPs. Likewise, the test-patterns are hard to make as well, given how many transactions across multiple threads need to be verified.
Cadence System Testbench Generator, System Performance Analyzer, Perspec, and Palladium work together to tackle these challenges by providing vast upgrades in speed and precision across the development process. No matter what your struggle is, the Cadence verification flow has a solution for you: if your emulation time is too long, use Palladium, if you’re struggling with test-pattern creation, Perspec can do that automatically for you with Portable Stimulus; and if the test bench creation itself is the bottleneck, Cadence System Testbench Generator can assist. All of these combine to create a comprehensive hardware emulation package.
In a collaboration with Cadence, Renesas developed a variety of features to improve their hardware emulation scalability. For one, they used AVIP (Accelerated Verification IP) instead of normal VIP (Verification IP), because AVIP is synthesizable to a hardware map and operates at HW speed. Two, AVIP has a C++ native interface, which is 10x faster than the SystemVerilog interface. The AVIP also has AMBA ATP (Adaptive Traffic Profiles) implemented in the master AVIP, which is useful for improving scalability as well. Lastly, Renesas and Cadence created support for concurrent traffic profiles, and more—and it’s compatible with Palladium and Perspec, too.
So, how has it worked out? The test, performed on an SoC with about 170 bus masters, had stellar results. In the assembling stage, Renesas saw a 5x efficiency boost using the System Testbench Generator and Cadence AVIP. When executing the simulation or emulation, they saw a 12x efficiency boost in the creation of test patterns, and a whopping 160x speedup in the actual simulation or emulation itself. Even the post-run analysis was faster, with a 16x speedup in calculating bandwidth and latency, time analysis between master and slave busses, and extracting the maximum and minimum bus performance with the System Performance Analyzer.
Renesas needed faster execution, easier testbench creation, and more efficient test-pattern generation, and Cadence stepped up to the plate and slammed a home run. In a partnership with Cadence, the two companies developed new, integrated approaches with scalability in mind, utilizing hardware emulation on Palladium with AVIP, automated testbench creation and analysis with System Testbench Generator and System Performance Analyzer, and scalable ATP test-pattern generation with Perspec’s Portable Stimulus.
Interested in this full system solution? Check out the System Testbench Generator, System Performance Analyzer, Perspec, and Palladium pages for more info.