Scalable OVM Register and Memory Package

Drawing on nearly a decade of experience, Cadence has just posted the first release of a scalable, open-source register and memory package for the OVM to the OVM World contributions area.  Modeled after the industry's first and most widely used "vr_ad" package for eRM, this new package is implemented in SystemVerilog but architected for multiple languages.  vr_ad is actively used by thousands of engineers worldwide and these e and SystemVerilog versions of the register and memory packaged will be merged in the future.  Along with the OVM package, Cadence is providing an IP-XACT parser so that verification engineers can use a standard input to manage registers and memory in complex OVM verification environments.

What is a Register and Memory Package?

A register and memory package is an important methodology extension providing additional observability and controllability in complex verification environments.  For example, in a typical processor-based system device registers are used to configure peripherals and are most often managed by the software running in that system.  For most modern systems, a directed test approach is out of the question so a randomized approach is needed to configure all of the system modes that need to be tested.  While the OVM is the ideal methodology in which to build the sequences and virtual sequences needed to verify the system, it still needs a way to reach into the DUT and configure the peripheral registers and system memory.  The register and memory package provides that access.

Requirements for Any Register and Memory Package

Any register and memory package must provide a set of capabilities to enable broad adoption.  First, the package must adhere to standards to assure the same interoperability as the host methodology.  Due to the complexity of modern systems, that means both the package itself and the register/memory descriptions that feed it must be open. Second, critical verification tasks including coverage, constraints, and back-door access must be automated to seamlessly integrate the package with the host methodology.  Third, the package needs to comprehensively support the SoC register types including direct, indirect, and mirrored.  Finally, the package must generate IEEE standard code leveraging the host methodology and scale to support hundreds of thousands of registers.

 Open, Scalable, and Infused with Experience

The customer-proven OVM register and memory package delivers on all of the key requirements.  Drawing from the success and momentum of the OVM, the package is IEEE compliant with the first implementation in SystemVerilog. Feeding the package are register and memory descriptions captured in the standard IP-XACT XML and a converter from XML to the package is provided with open-source deliverable.  Using IP-XACT is the open format defined by SPIRIT and assures multi-vendor interoperability of the register and memory descriptions.  Within the package verification engineers will find all of the critical technologies they need to manage registers and memory including coverage, back-door access, constraint management, sequence interfaces, single and multi-register manipulation, monitoring and more.  Maybe most important of all, the package is infused with more than five years of expert experience and has been validated by skilled verification users in live projects.

Getting Started, Deploying, and the Future

The OVM package is available and open for use today.  Cadence experts monitor the OVM forums, so feel free to post questions there or send direct questions to ovm_contributions@cadence.com for more personalized assistance.  Cadence and the OVM partners can also provide services and training to help you deploy the package in your group and company.  Consistent with the on-going evolution of the OVM, a few different packages are available on the OVM World contribution site further exemplifying the openness and vibrancy of the OVM ecosystem.  The OVM also has a proven track record of providing backward compatibility as it provides unified releases, so you can confidently adopt the Cadence OVM register and memory package knowing that your investment is protected while tapping the most experienced team and solution.

=Adam Sherilog