Serial NAND Flash: New Octal SPI Dual Data Rate Capabilities

11 Apr 2024 • 5 minute read

Serial NAND Flash

NAND Flash has been in a constant battle to prove its competitive edge over the more prevalent NOR Flash and find a path to break into the code storage market. Delegated for use as off-chip data storage[1], and passed over because of the high bandwidth requirements for code fetch, the NAND Flash has spent decades improving its sluggard image.

Targeting data throughput, Winbond, a leading NAND Flash memory vendor, introduced a high-speed continuous read capability in the Serial NAND devices with no gaps at page and block boundaries. Coupled with an innovative bad block management scheme and bringing ECC on-chip, susceptibility to errors being another drawback of the NAND Flash devices, the continuous read capability improved the Serial NAND Flash performance significantly.

To meet the increasing bandwidth needs of the automotive industry, Serial NAND Flash memories have evolved from a 1-bit slow clock SPI interface to fast clock speeds over 2-bit and 4-bit derivative SPI interfaces. Most recently, memory vendors added the Octal SPI interface to the Serial NAND Flash devices, which enables 8-bit wide high bandwidth synchronous data transfers at manageable clock speeds. In several cases, the Octal SPI interface is combined with double data rate capabilities.

Feature Details

The Octal SPI interface notably introduces additional pinout. The following is an illustration of a typical pinout for the Octal SPI interface added to the Serial NAND Flash devices:

Figure 1: Typical Octal Serial NAND Device

The Winbond Octal SPI Serial NAND Flash Memory with Double Data Rate capability can offer up to 240MB/s continuous read data transfer rates at 120MHz clock speeds. In this Octal SPI DDR mode, the legacy SI and SO pins are reused as SIO0 and SIO1, respectively, the /WP pin is reused as SIO2, and new SIO3-SIO7 pins are added to the package. There is also a new Data Strobe output pin, DS, that acts in conjunction with the read data to signal the host controller to latch data when running at the maximum DDR frequencies.

With the Octal SPI DDR interface, the data transfers over the Serial NAND wires are adapted to utilize the 8-bit wide data bus now available, along with the data strobe transferring data on every clock edge. The following timing diagram shows a typical data transfer over the new interface:

Octal SPI DDR NAND Data Transfer, the Data Strobe (DS*) is applicable for Read Command and driven by the Flash device to qualify the read data

Figure 2: Octal SPI DDR NAND Data Transfer, the Data Strobe (DS*) is applicable for Read Command and driven by the Flash device to qualify the read data

Verification Challenges

The changes in device architecture and design have presented design validators with scant options for rapid and effective verification of the feature within the high-demand and high-volume automotive application space.

The Octal SPI interface is intentionally pin compatible with the JEDEC Octal SPI specification (OSPI), but the existing OSPI verification memory models are NOR Flash devices and cannot model the SPI Serial NAND Flash architectures. The Serial NAND Flash verification memory models currently available in the market are x1, x2, or, at best x4 Quad SPI Serial NAND devices. While these could model the SPI Serial NAND devices architecturally, they cannot address the x8 Octal interface.

Moreover, the true advantage of the Octal SPI Serial NAND device is not attainable without enabling the Double Data Rate capability, and this feature does not exist for the SPI and Quad SPI Serial NAND devices. Even ignoring the DDR capability, a user cannot connect multiple copies of the SPI or Quad SPI Serial NAND devices to try and mimic an Octal device – the signaling is incompatible and such testing would be vastly inaccurate when compared with the functional as well as AC/Timing parameters of actual Octal SPI Serial NAND Flash memory devices from vendors.

The Cadence Solution

Automotive SoC and Flash Controller Silicon IP developers require a proven and reliable solution for the recent Octal SPI DDR update to their controller. Cadence, in partnership with the leading suppliers of Octal Serial NAND in the automotive space, including Winbond, crafted a solution to add Octal SPI DDR Verification support.

The Cadence SPI NAND Flash Memory Model now supports this new capability, which can be enabled in the Memory Model with a new configuration parameter. There is an additional configuration parameter that enables the Memory Model support for a Volatile Configuration Register that allows programming the correct Octal transfer mode. The Octal SPI DDR mode can be configured with or without DS (Data strobe). The feature includes support for the Vendor-specific Write Volatile Config Register command flow, and the DS-selection can be made via that command as described in the Vendor datasheets. All new command specifications, as described in the Vendor datasheets, are supported in the Octal SPI DDR mode. The command format follows the C-A-D (Command-Address-Data) sequence as specified in the Vendor datasheets.

The Cadence SPI NAND Memory Model is fully backward compatible, as specified in the Vendor datasheets. Depending on the configuration programmed by the user, the model can operate in 1-bit SPI Single Data Rate (SDR) mode, 1-bit SPI Double Data Rate (DDR) mode, 8-bit Octal SPI SDR mode, and 8-bit Octal SPI DDR mode.

NDA Prerequisite

This new feature is currently available via Non-Disclosure Agreements with Memory Vendors. This means that the feature can only be enabled via restricted SOMA files. If you are interested in enabling this Octal SPI DDR capability in the Cadence SPI NAND Flash Memory Model, you may contact the Cadence VIP Team by writing to us at talk_to_vip_expert@cadence.com or filing a service request on Support.Cadence.Com or by submitting a Datasheet SOMA request on Ememory.Cadence.Com and include the datasheet information from your Memory Vendor.

License Requirement

The Cadence Octal SPI DDR feature requires the MM_OSPIN Verification IP license key. Please contact your Cadence Field Team to obtain the necessary licensing. If you have any queries, feel free to contact us at talk_to_vip_expert@cadence.com.

More information on Cadence Memory models is available at Cadence VIP Memory Models Website.