Virtual Platforms to Shift-Left Software Development and System Verification

25 May 2022 • 5 minute read

System complexity has been increasing exponentially for years driving up the cost of verification. Increased hardware-dependent software functionality is a major reason for the growth in complexity. It has made verification and finding defects a challenging task. It is important to rectify the defects/failures earlier in the design process when they are less costly and take less time to fix.

Cadence Helium Virtual and Hybrid Studio helps to enable rapid creation of virtual and hybrid platforms and enables early software bring-up and concurrent hardware/software co-verification. It allows early software and OS bring-up, speed, accuracy, and a unified debug to validate hardware and software prior to silicon efficiently. Virtual platforms are more important than ever to verify purpose-built compute platforms. The shift-left verification methodology for early pre-silicon software bring-up and concurrent HW/SW co-verification helps reduce months off the schedules. However, setting these environments up requires some specific knowledge.

What is Shift Left?

Traditional chip development flow is on the left – where software bringup is done on the silicon after design verification is complete. In a shift-left development flow, the timeline is shortened by introducing a virtual platform to the process, as shown on the right-hand side, enabling software bringup to be part of the design verification.

It helps to run the software as part of the design verification. The timeline below shows that in the traditional flow, the product is shipped after sequential steps like verification, tape-out, software run, etc. However, in the virtual platform (SW-Enhanced) SoC Flow, an abstract model is introduced early on to let us do some software development earlier. The dependency is also very much on the hardware development to bring in a virtual platform of the final model early enough to provide value.

Similarly, while emulators and FPGA prototypes can be used to run software before tapeout without any new requirement to build a virtual platform, both require a complete design before they can run much in the way of software. A hybrid combines the early availability values of the virtual platform with the low overhead values of emulation and FPGA prototyping.

To build our hybrid, we start with an abstract model and incrementally make it more detailed as the design progresses. Eventually, we may bring in the emulators and prototypes to provide more detail at the highest possible performance. This hybrid process allows us to execute continuous validation as we incrementally bring up our system, incorporating new components as they are developed and integrated into the platform.

When is a Hybrid Approach Applicable

The virtual platform is available early in the process and allows a focus on the correctness of OS and middleware but may not give you the necessary level of performance accuracy. Additionally, pure virtual platforms often don't address the SoC level integration and verification very well because they tend to be abstract models, not the detailed RTL you're trying to verify. Emulators and the prototypes provide entirely accurate platforms as the use the RTL but may not show the performance needed for OS and middleware, especially in large processor environments.

Combining these two into a hybrid platform can address a complete software stack with enough detail for firmware and drivers and performance of OS and applications. One challenge is the apparent cyclic dependency of the virtual platform needing a final design while the final design is not complete until after the verification, which requires the virtual platform. This is addressed by the incremental software-driven methodology.

Typical Hybrid Platform creation and Software Bring-up Flow

The Cadence product suite and the methodology can create an environment that helps bring up the software where some of it is running on the virtual, some is running on the Emulator, and it all just works. The basic steps are as below

Create a new Hybrid platform
- Start with an example hybrid platform
- Save-As flow for the new hybrid platform
- Add/Remove virtual models( as needed)
- Configure parameters and bind ports
- Rewrite interrupt and memory map
- Add/ Remove RTL stubs(as needed)
- Configure Hybrid Adaptors for connecting to the new RTL design
Configure RTL to connect Helium Hybrid Adaptors
- Follow CPU Architecture Example including CPU RTL wrapper details and configuration options
- Integrate the interrupts as per the example GIC wrapper
- Add Smart memory for performance
Build and Run Linux on the Hybrid Platform to enable SW debug

This hybrid environment can be built using either the FPGA prototype or Emulator that contains the detailed RTL code.

Typical use cases are

Bring up and test Linux and drivers
Bring up and test Android
Targeted benchmarks and performance optimization
Critical application bring-up.

Cadence Helium Virtual and Hybrid Studio

The Helium Studio enables early software bring-up for hardware-software co-verification and debugging. It provides comprehensive support for platform assembly, enables the creation and debugging of virtual models, and offers a rich library of pre-built virtual models and hybrid adapters. It is Architected to natively integrate with the Cadence verification engines, including the Palladium Z2 Enterprise Emulation Platform, the Protium X2 Enterprise Prototyping Platform, and Xcelium Logic Simulator. It accelerates system development by verifying embedded software/firmware on pure virtual and hybrid configurations starting before the RTL is ready.

Engineers creating next-generation designs, including mobile, automotive, and hyper-scale computing applications, need to validate software on a pre-silicon platform to ensure design success and meet time-to-market schedules. The Helium Studio allows designers to build high-quality virtual and hybrid SoC models. Through the native integration of the runtime software engine of the Helium Studio with the Palladium Z2 platform and the Protium X2 platform, the Helium Studio provides software developers with a uniform debug experience from a virtual model to RTL.

Conclusion

The Cadence^® Helium Virtual and Hybrid Studio gives the desired speed for early pre-silicon software bring-up and the accuracy for pre-silicon hardware/software co-verification, all with a unified, embedded software debug experience and native integration with Cadence's Xcelium, Palladium^®, and Protium verification engines. Using the system, verification with a virtual or hybrid model of the SoC is not just orders of magnitude faster than verification with a pure RTL model; it enables early software bring-up before the RTL is available.

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