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Challenges and Applications in a 3D World

26 Aug 2014 • 1 minute read

As the 3-D memory market matures,  it continues to incubate new application opportunities and confront new challenges.

Some of the challenges faced by 3D memory adoption range from technology to cost and design. 

On the technology front, many of the initial challenges around the interconnect reliability and scalability of through-silicon vias (TSV), interposer development and chemical mechanical polishing (CMP) have been addressed through programs like TSMC’s Chip-on-Wafer-on-Substrate (CoWoS) program.  Thermal management is still a challenge facing adoption, especially for full 3D implementations. silicon waferThese programs also have helped to mature and improve the test methodologies, supply chain and design flow issues that loomed very large at the initial stage of 3D adoption.

The third challenge still being faced by the industry is cost. Cost is still a major driving factor for adoption whether it is an FPGA, SoC interposer or full 3D based implementation choice.   

Looking at the rate of adoption, four primary segments leading the adoption are gaming, networking, high performance computing and mobile.  All of these segments began initial adoption in 2014:  

  • Adoption in the gaming segment began in earnest with 2.5D and has been projected to continue to full 3D by 2016.  As a consumer-based segment, gaming is highly driven by both cost and performance.
  • Adoption in the networking segment began for both 2.5D and 3D solutions and is predicted to continue on a path to full 3D adoption by 2016. 
  • High performance computing adoption has such extreme performance needs that this segment has initially started with full 3D solutions.
  • The mobile segment.  As this is also a consumer segment driven primarily by cost and performance, the initial adoption has been focused on 2.5D solutions and is projected to continue on a path to full 3D adoption by 2018.

In order to take advantage of these new technologies, we must confront another challenge: ensuring we have comprehensive simulation and verification models that enable not only verification against the standards but that also enable what-if analysis for complete exploration based on the target application. Cadence has been an early supporter of all of these 3D technologies and provides advanced verification models as part of its Memory Model Portfolio.  

Scott Jacobson

Related stories:

--Cadence Announces Verification IP for MIPI SoundWire™ and C-PHY

--Cadence PCIe Solutions: Configurable, Compliant, and Low Power

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