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Microsemi has been evaluating a unique feature in Xcelium System Verilog UVM Dynamic Test Load for some time now, and they shared their thoughts on it in a paper presented at CDNLive San Jose April 2018.
One of the fields Microsemi operates in is the realm of optical networking. In optics, a given sensor’s input can vary wildly, but the way the input is processed is largely the same. Thus, a wide variety of tests are required to fully test a design for an optical sensor’s chip, and that implies the need for a lot of simulation.
To reach maximum coverage, though, they still need to be verified thoroughly. How did they solve this issue? Testing each input, and recompiling in between each test, takes a very long time.
In comes SystemVerilog / UVM Dynamic Test Load!
Before this update, SystemVerilog was very slow to debug: it requires you to recompile after each test. Plus, it only has simple peek, poke, and force options. SystemVerilog still has these limitations, but now Xcelium doesn’t! Dynamic Test Load is a solution within Xcelium that solves those issues making SystemVerilog UVM easier to use.
What was added that makes this new update so cool, then?
SystemVerilog UVM Dynamic Test Load allows you to load new UVM sequences via SystemVerilog packages into a saved snapshot (saved simulation state), and call testbench functions when that snapshot is reloaded.
There’s two types of dynamic snapshots: a dynamic base snapshot (DBS), which is the snapshot saved at time zero, and a dynamic test snapshot, which contains whatever new SystemVerilog packages you want to use. Use the $save("snapshot_name") system task in the testbench to create a snapshot and use the xsim tcl save command during runtime (xrun> save snapshot_name).
Dynamic Test Load is still pretty new, so new features are being added all the time. Right now, we’re working on support to save your snapshot into a different path than the default—that said, Dynamic Test Load does support saving into a different library at this time. Be wary of increases in the size of the CDS library caused by multiple jobs writing to the same library —in the future, there will be a bundled tool that can copy this library, minimizing the risk of the original library corrupting.
How do you use SystemVerilog UVM Dynamic Test Load? First, compile the DUT and the stable parts of your testbench with incremental elaboration (MSIE). Save a dynamic base snapshot at time zero. Make sure each test case and all sequences that may change are in their own packages. Now, you’re ready to save and load snapshots as you need.
Doing this the old way, where everything was re-elaborated every time, would take around five minutes. However, with Dynamic Test Load, you can drop that time done just one minute.
This can speed up your RTL debug turnaround time by around 90%, with an average time to failure in simulation at six hours. Overall, it can halve your development time!
If you’re ready to start cutting your development time in half, check out the presentation given at CDNLive by Microsemi here.