Summary of a Really Busy DVCon Week

Joe Hupcey has done his usual fine job of documenting DVCon (day 1, day 2, day 3) but I want to take a step back and summarize what has surely been one of the busiest weeks ever for the Cadence functional verification team. 

Our DVCon activities included a booth in the Expo, an OVM tutorial, an OVM lunch with three customer presentations, a panel on mixing simulation and formal, and several technical papers. 

Also, we participated in four press releases, each involving major activity around the OVM ecosystem and OVM-enabled Cadence products:

• OVM Extended to Efficiently Manage Coverage Metrics
• Cadence Extends the Open Verification Methodology Beyond SystemVerilog to Include SystemC and e Language Support
• Cadence Incisive Verification IP Portfolio Delivers 'All-in-One' Flexibility and Higher Value for SoC Developers
• VeriEZ’s community version of Rule Checker to support broad OVM momentum

Of course, we were also busy holding a wide range of formal and informal meetings with customers, partners, and competitors who were in San Jose for the show this week.

 I plead guilty to tooting our own horn a bit here, but I look back on this week with personal pride and a great sense of excitement about how rapidly the OVM is expanding in breadth and depth.

 I also want to make sure that our loyal readers (and we know from the Web stats that we have them!) didn't miss any of the key announcements or activities this week.

 I'm looking forward to the weekend for recharging; hope that you can do the same.

 Tom A.

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