Synthesis Really DOES Need to Change

A great article appeared in Chip Design a few weeks ago written by Tets Maniwa, “Synthesis Needs to Change to Serve Modern Chip Design”.

Tets Maniwa is sharp guy. (Those of you designing ICs in the mid/late 1990s probably remember a wonderful magazine called “Integrated System Design” (ISD). ISD was one of the premier IC design trade-pubs around at the time, and Tets was lead editor.) Whenever Tets writes something, it’s worth reading.

The thesis of Tets’ article is that with mainstream IC process-technologies well below 90nm, there’s a “synthesis bottleneck” associated with productively getting enough gates, with enough density, working in silicon. He describes how people from IBM, LSI, Renesas and other companies are having to deal with problems related to design size and complexity, hierarchy and partitioning, long run times, insufficient throughput, and last-minute changes (ECOs) before tape-out.

While the article notes that “Next generation tools will need better coupling between RTL and physical issues, larger capacity, multivariate analysis, and optimizations over a wider range of parameters.”, there’s another whole dimension/approach toward solving the “synthesis bottleneck” that the article overlooked.

What about raising the level of abstraction for design-entry, while still maintaining a tight coupling with the back-end? In the article, Tets makes a passing reference to this: “While there was hope for the potential of C synthesis (and there are several of those solutions in the market today) the vast majority of IC design teams still start by writing the RTL themselves because of quality of results concerns in high end chips.”

The implication is the proof/value of HLS technology is somewhat dubious and its users remain “on the fringe”. Obviously, Tets needs to learn more about C-to-Silicon Compiler (CtoS)! If he had interviewed any knowledgeable people at Cadence for their insights, he would have learned that Cadence architects understood about this “synthesis bottleneck” for long time, and this was the reasoning underlying the basic architecture of C-to-Silicon Compiler, which is fully integrated with RTL Compiler.

As many of you know, from a technology standpoint RTL Compiler has the tightest/most advanced back-end/physical linkages of any logic-synthesis tool (yes, all of you DC aficionados out there, even more the DC). By architecting CtoS from the ground-up with “RC-inside”, CtoS architects created a solution that raises the level of abstraction for design-entry, while maintaining the back-end/physical linkages required for implementing designs at 65nm and below. As Ron Wilson pointed out in another article earlier this week, “ESL tools need to see what synthesis will do in order to create useful RTL.” I would go even further, and claim that ESL tools will eventually need to see what floorplanning, layout, and P&R will do in order to create the best-possible RTL. Going forward, CtoS plans to leverage capabilities like RC-physical and clock-tree synthesis, enabling high-level designers to take into account IC layout, congestion, and other physical characteristics during the microarchitecture exploration process, and thus generate IP that not only meets even more rigorous timing and power constraints, but is also more reusable (this is because the “golden-source” is no longer RTL, but SystemC/TLM.

For all these reasons, I really think Cadence and CtoS are uniquely positioned to benefit from the evolution we’re starting to see from RTL-driven to TLM-driven design.

Steve Svoboda