DATE Spotlights System Development University Investment in Europe

In this guest blog Markus Winterholer, R&D engineer at Cadence, explains why he's attending the University Booth at the DATE Conference in Grenoble, France March 14-18.

I’m getting ready for a busy upcoming week with DATE conference in Grenoble, France. Besides organizing a workshop and a panel about embedded system debug and test, presenting Cadence ESL tools at the Europractice event and helping representing Cadence at GlobalFoundries (booth 1& 2), I’m squeezing customer visits into my tight schedule. I’m already created a short list of presentations I will attend at this always worth visiting conference.

Despite a busy day, however, I’m already planning ahead to spend enough time at the University Booth on the exhibition floor. This is not only because Cadence is a co-sponsor of this event, which I found out lately, but because it is a great opportunity to discuss upcoming solutions and to get in contact with the people behind these research projects.

Since a visit at DATE has to be planned ahead, I already know when I will stop by at the University Booth. This year I picked three topics. First, power estimations and optimizations; second, methods to shorten time to market for multi-threaded and multi-core applications; and last but not least, a very interesting high level approach to combine simulation and formal verification. Starting with the later presentation titled “Demonstration of a Coverage Driven Verification Environment for UML Models of Systems-on-Chip” I’m  interested in learning how the authors enhanced simulation with static analysis of UML models and model checking techniques.

Two presentations are promising solutions if your design complexity increased lately due to the usage of hundreds of processors, instead of just one as in the good old single core SoC days. The first one presents “Daedalus” – a system-level flow that does auto-parallelization of sequential programs as well as system-level simulation and high level synthesis. The second presentation is from TIMA, in Grenoble, about their solution “VOCIS” -- a simulation model that enables quantitative comparison of interconnect architectures regarding power, performance and reliability.

Power and energy optimization is an important topic for Cadence R&D, so  hopefully will have time to chat with Kyushu University to learn how memory access optimizations in embedded systems can improve power consumption. If I miss the booth of Open-PEOPLE to learn how their power and energy optimization platform and estimator is working I can check that later on their home page.

So take the chance to say hello next week in Grenoble, France and leave a comment if you visited University Booth at DATE.

Markus Winterholer