System Realization Webinars Start Sept 8th

Starting September 8th Cadence will be hosting a series of webinars about various topics in the area of System Realization. Several of these webinars will be led by members of the System Realization Alliance, sharing their particular views and contributions of the industry, and their connection and interoperability with Cadence methodology and tools.

Readers who want to learn about adoption strategies and benefits of leading edge ESL methodology, modeling, synthesis and verification can do so efficiently in these technically-based webinars.

The webinars all run Wednesday at 10am Pacific time, starting Sept 8th.The first webinar will be led by XtremeEDA, followed by CircuitSutra, Imperas, and Calypto Design Systems, Inc.

Participants can register here. Recordings will be available afterwards if you can't make that particular time.

XtremeEDA - Sept 8th, 10am

ESL has come a long way since its formal identification several years ago; however, it has not made the sweeping changes that early promoters expected. This talk will look at a few of the reasons why ESL adoption has been slow, and show why a new approach using a holistic methodology is changing the rate of adoption. This includes a look at what drives real design, the fundamentals of change, and some of the missing elements for a realistic approach to ESL. In particular, this new methodology embraces System Realization holistically—from architectural investigation to gates, embracing design, verification, and validation with an emphasis on reuse of all components.

CircuitSutra - Sept 15th, 10am

In this presentation, we will talk about various SoC modeling standards and how they work with Cadence tools to enable the TLM-driven design and verification methodology. The SoC modeling standards include: OSCI SystemC IEEE 1666, OSCI TLM 1.0, OSCI TLM 2.0, OSCI SystemC synthesizable subset draft, STARC TL guidelines, and the OCP-IP modeling kit.

Imperas - Sept 22nd, 10am

This presentation will show how the integration of Incisive SystemC simulation, Incisive Software Extensions, processor models from OVP, and software simulation and verification tools from Imperas enable software functional verification. When the virtual platform is coupled with Incisive Software Extensions and Imperas software verification tools, software engineers can verify the functionality of code (such as drivers) in the context of the complete OS running on the platform. This software verification capability, including white-box functional coverage, has not been possible until now. Key new technologies from Imperas (fast simulation and verification tools) and new flows (the integration between Cadence and Imperas tools) have made this possible.

Calypto Design Systems, Inc - Sept 29th, 10am

During this webinar, Calypto will describe its shared vision and provide a complete overview of how its sequential analysis-based products play a key role in today’s new era of application-driven design. The discussion will highlight the advantages of Calypto’s SLEC System-HLS product, which comprehensively verifies the RTL generated by high-level synthesis tools using its patented sequential analysis technology. In addition, Calypto will review the benefits of incorporating Cadence C-to-Silicon Compiler as well as how SLEC enables the broader adoption of TLM-driven design. Calypto will also provide a detailed review of its sequential analysis-based PowerPro products, which deliver both dynamic and leakage power savings and enable customers to produce the most energy-efficient designs possible.

Steve Brown