System to Silicon Verification – CDNLive Gives a Reality Check on How Hardware and Software Meet

Ever since switching from being a hardware/software chip developer to being an enabler with tools in EDA and embedded software, I was part of a team working towards methodologies and tools to improve the interaction of hardware and software. In December last year -- 15 years in -- I summarized a great year 2012 in a blog "System Design 2012 - Real Users Achieving Real Results!". Well, next week (March 12-13, 2013) CDNLive in San Jose will kick off, and I am happy to report that we will have again a great lineup of users and partners presenting their approaches to dealing with verification from systems to silicon, in most cases involving significant amounts of software in the process. As a special perk, we will have Wednesday lunchtime discussions with our product management and R&D team on special focus topics centered around system to silicon verification -- so I hope to see you there!  

As a leader of the product management team for the System Development Suite I am especially thrilled to see how the four pillar engines -- virtual prototyping, RTL simulation, acceleration/emulation and FPGA based prototyping -- are growing together. With our key partner ARM, we recently showed at Embedded World how we connected Palladium XP and a quad core A15 Virtual Prototype for early hardware/software development and verification. But there is more - and you can see most of it at CDNLive next week! The figure above gives an overview of the engines and their connections, and here is some of the key content to be presented next week:

• Starting with pure Virtual Prototyping, ARM will show in session SYS204 "How ARM® Software Development Tools can Accelerate Your Time To Market". Focusing on software testing, Imperas will show in session SYS205 "Virtual Platform Based Software Testing for ARM-Based Systems" how to apply transaction-level based techniques.
• Showing the value of connections of Virtual Platforms to RTL - both in simulation and hardware acceleration - our IP Team at Cadence will show their use of virtual platforms in session DVSY104 "Using Virtual Platforms for Firmware Verification". BlueSpec will illustrate in session SYS203 "Bridging Virtual Platforms and FPGA-based Prototypes for Early, High-Speed, Accurate Software Development" how to connect our Virtual System Platform (VSP) and FPGA based Rapid Prototyping Platform (RPP). Similarly to what we showed with ARM at Embedded World, we will show in session SYS303 "Improving Speed and Debug-ability of Emulation / Prototyping Phase of ARM SOC Development" how to connect VSP with the Palladium XP accelerator/emulator.
• Acceleration and Emulation will be prominently discussed in several customer sessions. Freescale will show performance validation in session SYS102 "Case Study: Using Cadence Palladium for SoC Performance Validation and Analysis". Intel Corporation will show in session VER102 "UVM-e Based Validation IP re-use for Emulation" their use of UVM with emulation. AMD will provide an update on in-circuit acceleration in session SYS104 "Enabling a New Paradigm of System-level Debug Productivity While Maintaining Full In-circuit Emulation Performance".
• We will hear an update on recent successes Samsung had with Accelerated Verification IP (AVIP) in session SYS207 "Solid State Drive Verification and Driver Integration Using PCI Express Accelerated VIP". A key topic for emulation in System to Silicon Verification is Low Power, which we will show in session LP204 "Dynamic Power Analysis with Palladium" and LP201 "CPF Low Power Verification Using Palladium Systems". UVM and assertions in acceleration will be shown in session SYS304 "FastTrack Your UVM Debug Productivity with Simulation and Acceleration" and SYS206 "Shortening verification cycles and increasing chip quality with accelerated coverage". As already mentioned above, connections to virtual prototyping will be shown in session SYS303 "Improving Speed and Debug-ability of Emulation / Prototyping Phase of ARM SOC Development."
• Incisive Verification will focus on various aspects like UVM, low power, verification planning, debug and gate-level simulation in a set of focused sessions including VER103 "Are you Still Building Test Benches?" presented by Sonics, VER206 "UVM Multi-Language: Technology and Reference Application", VER202 "Best Practices In Verification Planning", VER203 "Improve Debug Productivity from Hours to Minutes Using the Incisive Debug Analyzer", VER205 "Low-Power Verification in a UPF to CPF Flow", VER201 "Addressing Renewed Gate Level Simulation Needs at 40nm and Below" and VER104 "Advances in Client-Server Technology for More Verification Automation"
• Verification IP can't be missed with sessions on DDR4, non-volatile design, Super-Speed Interconnect and performance debug in sessions DVSY105 "DDR4 System Design Challenges" presented by Teledyne LeCroy, DVSY102 "Non-Volatile Design Verification Challenges", DVSY103 "Is SSIC (Super-Speed Interconnect) - Revolutionizing the Mobile Design?" and DVSY101 "Analyzing and Debugging Performance Issues with Complex ARM CoreLink System IP Components" presented jointly by ARM and Cadence.
• Further updates from customers and partners will be given on FPGA based prototyping. Freescale will provide an update is session SYS202 "Implementation of a Multi-threaded 64-bit Power Architecture Core on the RPP FPGA-based Prototyping System", I already mentioned above BlueSpec's update in session SYS203 "Bridging Virtual Platforms and FPGA-based Prototypes for Early, High-Speed, Accurate Software Development" and we will also provide a general update in session SYS201 "FPGA-based Rapid Prototyping - Help or Distraction for Embedded System Development?"
• Finally, rounding up the full picture of System to Silicon Verification, you can catch session SYS301 "High-level synthesis introduction to C-to-Silicon Compiler" to see how to further optimize verification using high-level synthesis. My own session SYS101 "System to Silicon Verification - How It All Fits Together" will put everything in perspective on Tuesday morning.

So bottom line, this will be an exciting CDNLive for System to Silicon Verification next week. I am looking forward to seeing you for the sessions above, for lunches with R&D and for demonstrations during the exhibition. 

Frank Schirrmeister