The barriers to efficient System Level Design and Verification

The EDA industry been doing system level design and verification for years; we just haven't been doing it very well.  Most all of us do hypothesize about what might be the ideal configuration of hardware and software to deliver our application in a cost effective way.

However, becuase there are so few tools we can use to test our hypothesis, we are soon reduced to taking a leap of faith in to commit to a particular mapping of the problem we are trying to solve onto the hardware and software solutions we are familiar with, or those we feel confident we can easily build, rather than spending any qualitative time on researching alternatives that while having perhaps more up front costs, could possibly result in the best implementation.

One reason we don't spend much time here is because the reward for the time spent is so so small.  Without a link to implementation that we can use to test our guesses, we have to make so many assumptions about the feasibility of various possible implementations, each which are off by a factor of 20%, that taken together our overall estimate's compounding of these myriad assumptions leaves us with very little confidence that the entire system we are considering could even be built.