The Evolution of MIPI DSI

The MIPI DSI specification has come a long way from the days of its early introduction targeting mainly mobile applications to today, where it is finding use in very different industries like automotive and IoT. This evolution has been further expedited due to the introduction of the C-PHY.

The Display Serial Interface (DSI) is a specification by the Mobile Industry Processor Interface (MIPI) Alliance, which was aimed at reducing the cost of display controllers in a mobile device. It is commonly targeted at LCD and similar display technologies. It defines a serial bus and a communication protocol between the host which is the source of the image data, and the device which is the destination of the image data.

The main differentiator between the DSI and DSI-2 versions is the addition of support for MIPI C-PHY in the DSI-2 specification. MIPI C-PHY, which was released as v1.0 in 2014, is designed to connect the camera and display modules to an application processor. Despite the very different nature of the PHY, the interface is backwards compatible with the existing MIPI Alliance Camera Serial Interface (CSI-2) and Display Interface (MIPI DSI) systems, so it allows system designers to easily scale these ecosystems to support higher resolution image sensors and displays, while at the same time keeping power consumption low. It also supports soft configurability of lanes within a link to optimize bandwidth and minimize pin count. MIPI C-PHY can be implemented with MIPI D-PHY on the same device pins, which allows connections to the companion device with either PHY technology.

The MIPI C-PHY specification was developed to reduce the interface signaling rate to enable a wide range of high-performance and cost-optimized applications, such as very low-cost, low-resolution image sensors, sensors offering up to 60 megapixels, and even 4K display panels. It accomplishes this by moving away from the conventional differential signaling technique on two-wire lanes and instead introducing 3-phase symbol encoding of almost 2.28 bits per symbol to transmit data symbols on 3-wire lanes, or “trios” where each trio includes an embedded clock. Three trios operating at the MIPI C-PHY v1.0 rate of 2.5 Gsym/s achieve a peak bandwidth of 2.5 Gsym/s times 2.28 bits/symbol, or about 17.1 Gbps over a 9-wire interface that can be shared, if required, with the MIPI D-PHY interface.

Today, the range of products that use MIPI DSI is vast and includes everything from phones and cameras to IoT, automotive, and even industrial. A quick search for MIPI products reveals a host of devices that include automotive MIPI DSI bridges to embedded DisplayPort (eDP), 4k2k VESA eDP to MIPI bridges that can be used in tablets, phablets, and portable gaming devices, and even DSI transmit designs that enable embedded designers to utilize low-cost screens with embedded processors in IoT applications.

Cadence, a contributing member of the MIPI alliance since 2007, has been an industry leader of MIPI DSI verification IP and has watched this evolution up close and personal from the time it was first introduced to the present date with its ever widening reach. Cadence DSI VIPs have been used by tens of customers over hundreds of products, and are a proven display interface IP solution that will enable you to integrate the MIPI DSI interface into your application with lower risk and lower cost while reducing time to market for mobile, automotive, and IoT SoCs. Please visit our MIPI DSI-2 page for more information.

From mobile displays to automotive, industrial and beyond – DSI, you’ve come a long way, baby!

Priya Balasubramanian