There's Another Simulation Failure! New SimVision Features Can Help

Simulation failures are seen quite often in design verification.   Fortunately, with the new Cadence Silicon Realization approach, you'll have the tools necessary to quickly get back to simulating.  The complete solution for determining what is causing your simulation to fail is SimVision, part of the Cadence Incisive Enterprise Simulator. 

You probably saw the recent press announcement, "Cadence Boosts Verification Productivity for Complex FPGA/ASIC Design."  It's talking about the holistic approach to Silicon Realization through metric-driven verification (MDV).  The productivity in verification can be measured in several ways.  Many advancements have been made in simulation engine performance, faster turnaround times, smarter verification through MDV and so on. 

But, when it comes down to productivity in debug, it gets personal.  Now it's actual time that you spend at the computer trying to figure out how or why the simulation failed.  That's where I hope you will find that the advancements we're making with SimVision will help you to do your job better by being more productive.

Design verification environments are getting more complex.  They may contain several of the standard IEEE languages in the industry today including Verilog, VHDL, SystemVerilog, SystemC, e, and PSL as well as the emerging Accellera Universal Verification Methodology (UVM) 1.0.  Having the ability to debug your entire verification environment together with one analysis and debug tool is a huge benefit to your productivity. 

It gets more complicated than that, though.  It's not just these languages that add to the complexity.  There are also the challenges you will face when you include capabilities such as mixed-signal, low-power and formal analysis into your methodology.  Add to this the fact that you would want to use the same analysis and debug tool whether you're working with an architectural model or a gate-level simulation.  That's an amazing amount of complexity, but that's also reality.  You want one holistic approach to your verification. 

New SimVision Capabilities

Below is a selection of some of the new capabilities in SimVision.

Within SimVision's source browser we've improved the ability to expand macro definitions and "include" files.  Also, the design file search window allows you to search for a string in all of your design source files, which could be a big time saver.

The design browser has been enhanced to help you in viewing not only the design, but also the entire verification hierarchy including objects and data members.  There are also new capabilities within the design browser sidebar for searching scopes.

The watch window has new features including the display of additional information about the objects, enhanced tooltips, breakpoints and improvements in how you control the information in the window.

The waveform window has now implemented one of the most popular former plug-ins, referred to as counting edges.  It will not only count the positive, negative and total edges but will also provide information on the time high, low and duty cycle.  Another new feature is the ability to lock the scrolling of multiple waveform windows, both vertical and horizontal scrolling.

The schematic tracer has enhanced the color of the trace path so that it maintains its color during the entire session.  Also the display of the pins that are not part of the trace path can now be removed to make for easier analysis. 

You are now able to annotate the register window with not only lines, boxes, shapes and text but also with images.  If a picture is worth a thousand words, then this is an obvious benefit when trying to make the display more meaningful.

Plug-ins have always been a great way to turn on new features and capabilities in SimVision.  There is a new plug-in for viewing dynamic objects with the data browser.  You should find this very useful for displaying things such as classes, queues and dynamic arrays within an OVM/UVM environment.

Another plug-in is used for creating a group scope within the design browser and waveform windows.  This will help to create a group for all of the signals and variables in a particular scope. 

There's also a new plug-in to assist you when you are trying to do a comparison between two databases.  This new Interleave capability is used within the SimCompare functionality for doing an absolute comparison.

This is just a glimpse into some of the new capabilities in SimVision.  For further information on all of these features and enhancements, please refer to your product documentation.  There's a "What's New" document that will provide the links to the above features and much more.

There's an excellent workshop that is included with the release on SystemVerilog and UVM debug.  It can be found in the Incisive Verification Kits under the Universal Verification Methodology topic.

So the next time you hit a simulation failure, which is likely soon, take advantage of the latest features of SimVision to debug it and get you back to simulating quickly.  It'll make you more productive when it really counts.

Jim Kjellsen