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RISC-V, an open specification of an Instruction Set Architecture (ISA), which was designed to be scalable for a wide variety of applications has been enjoying wide-spread adoption in the industry.
TileLink is a free and open standard chip-scale interconnect protocol designed for RISC-V processors and beyond (could be used with other ISAs as well). It’s a fast scalable SoC communication protocol designed to connect multiprocessors, co-processors, accelerators, DMA engines, and a slew of other devices.
Any RISC-V SoC can use TileLink protocol to implement coherent memory-mapped access to memory and other slave devices. It is a master-slave point-to-point protocol in which operations are composed of messages sent over five (5) independent channels. TileLink offers many attractive features like support for out-of-order completion, by-design deadlock-free operation, and support of cache-coherent shared memory.
TileLink protocol has three conformance levels with increasing complexities which makes it possible for the protocol to be used for simple slave devices as well as for devices that require support for coherent caches. The conformance levels are:
Serving the growing need of TileLink functional verification, Cadence introduced a new TileLink VIP in its Verification IP Catalog (VIPCAT). Cadence TileLink VIP is a comprehensive Verification IP solution with support of all three conformance levels and is compliant to the latest specification versions.
TileLink VIP has the following key features:
We invite you to start using TileLink VIP and enjoy its power in TileLink protocol verification.