TLM-Driven Design and Verification Solution

At this week's CDNLive! Japan we made an important press release announcement about our new TLM-driven Design and Verification Solution, and delivered the first Techtorial covering the technology and methodology. The solution combines C-to-Silicon Compiler (CtoS), Incisive Enterprise Simulator (IES), Incisive Enterprise Manager (IEM) to enable customers to use transaction level modeling (TLM) for design and verification. The unified methodology is built upon the OVM and SystemC industry standards and brings together the benefits of high level synthesis and metric-driven verification.

The NEWS in this announcement is:

• A new TLM-driven Design and Verification Methodology (TDM)
• CtoS automatic migration of C/C++ to SystemC for methodology enablement
• CtoS memory compiler integration API and optimization, and
• Solution integration of CtoS/IES for side-by-side SystemC/RTL debugging

The main BENEFITS of this solution are:

• Improved designer productivity and QoR
• Reduced functional verification cycles
• Increased design and verification IP reuse

Some of the things being said about this announcement:

• "We like SystemC for high level synthesis since it includes everything in C++ and is the industry-standard way to describe hierarchy, concurrency, fixed-point arithmetic, and bus protocols -- more importantly, for designs with any significant control logic, the C-only-based tools simply do not work. We chose Cadence's C-to-Silicon tool because it supports SystemC." Jen-Chieh Yeh, IP design manager at Industrial Technology Research Institute
• “We have been employing high-level synthesis and TLM verification for several years, and verification methodology has proven to be quite challenging,” said Raimund Soenning, hardware development manager, Graphics Competence Center, Fujitsu Microelectronics GmbH. “The Cadence methodology addresses the challenges we’ve experienced applying Metric Driven Verification from TLM through RTL, and mixing the two. We see significant opportunities to increase the reuse of our design and verification IP by following the comprehensive Cadence methodology.”
  Raimund Soenning, Hardware development manager, Graphics Competence Center, Fujitsu Microelectronics GmbH
• “An increasing number of our customers are adopting TLM for efficiency and are joining the growing ecosystem of companies exchanging IP, driving our verification IP roadmap. However, we do expect companies will continue to use RTL legacy code for quite a while, as the industry transitions to a TLM-based approach. The Cadence solution addresses the very important requirement of mixed TLM and RTL designs, and uniquely combines design and verification into a unified methodology.”
  Stylianos Diamantidis, CEO of Globetech Solutions
• “The technology has been maturing at a rapid pace. Market adoption is showing signs of taking off, and methodology is critical for enabling customer success.”
  Gary Smith, Gary Smith EDA
• "This year we've seen growing demand for our SLEC System-HLS products, driven in part by Cadence's aggressive push to move the industry toward SystemC and TLM-driven Design and Verification. We are collaborating closely with Cadence at key mutual customers to establish a robust flow and methodology for optimally combining simulation-based and formal-based design verification around Calypto’s SLEC products and Cadence's C-to-Silicon and Incisive solutions."
  Tom Sandoval, President and CEO, Calypto

Cadence TLM-driven design and verification summary:

• Unified solution
  • Methodology for industry-standard SystemC
  • Datapath, control and protocol synthesis and ECOs
  • OVM-based multi-level verification
• Ecosystem integrations
  • Xilinx and Altera FPGA flows
  • Calypto sequential logic equivalence checking
  • ARM processor IP model SystemC interoperability

Steve Brown