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It won’t be incorrect to say that the transport layer of a USB4 router is the backbone of it. It is a layer that holds all the various other layers together. It provides the very essential services like paths and routing for tunneled traffic, various types of flow control, link management, which are some of the core features that make a USB4 router work the way it should.
A path is like a virtual wire, which is a unidirectional logical end-to-end connection. This concept works in conjunction with the programmable routing tables at each adapter. With help of these the tunneled traffic find their way through the routers to their respective destination adapters.
While all tunneled traffic goes through the transport layer jumping from one adapter to another this traffic is flow controlled too. There are various types of flow control mechanisms defined which can be used depending on the type of tunneled traffic.
The flow control mechanism also has a lot to do with the number of buffers that adapters implement for each path. The number of buffers that are available at an ingress adapter for a path determines how many packets it can take in at a time from the corresponding egress adapter for that path. But the egress adapter at one end of the USB4 link must be aware of how many buffers does the ingress adapter at the other end of the link has empty. This information is shared by use of the link management packets.
Robust working of the flow-control mechanism is critical to the functioning of the tunneling through the router's hierarchy. It gives rise to many verification scenarios for which a USB4 router design must be verified for.
For ex., verifying an adapter for conditions of credit starving, meaning that the egress adapter should not send traffic for the path for which there are no credits advertised in Credit Grant records.
Verifying transport layer of a router design is quite an involved task and needs verification from several aspects mentioned above.
Cadence has a mature Verification IP solution for the verification of various aspects of the transport layer of a USB4 design, with verification capabilities provided to do a comprehensive verification of it.