Users Employ Specman Constrained-Random Verification for Complex IP

Two recent customer examples have shown the effectiveness of Specman constrained-random verification for complex SoCs. Raimund Soenning, manager of hardware development for the Graphics Competence Center at Fujitsu Semiconductor Europe (Germany), and Sarmad Dahir, ASIC designer at Ericsson (Sweden), have transitioned from traditional verification methods to a Specman-based, constrained-random, coverage-driven verification approach.

Verification of complex SoCs and IP blocks introduces new levels of challenges such as controllability, planning and progress tracking. Traditional verification methods such as directed testing cannot address these challenges. So, customers such as Soenning and Dahir have transitioned from direct testing approaches to a constrained-random, coverage-driven approach. This makes it possible to stress the RTL to a much higher extent with full controllability, automatic generation of tests, coverage ranking, and metric-driven verification to improve overall verification productivity as well as product quality.

Two recent Industry Insights blogs captured the following quotes:

"Random testing makes things easier, because you won't have to target every possible scenario," Dahir said. This translates into a time savings -- perhaps 30 percent for the overall verification process, Dahir said.

"We have much better confidence that our verification is actually good," Dahir said. "So it's not only the time we're saving, it's the quality of the verification we're getting."

You can get to interesting scenarios and find bugs in your design much more quickly," Soenning said. Also, maintenance expenses are lower. "In Specman I need to maintain maybe 5 or 10 tests for one IP. In directed testing I need to maintain hundreds of files."

Soenning also said his group has experienced a "tremendous productivity gain" with Specman verification IP for such protocols as AHB, AXI, and PCI Express.

Read the full blog interviews: